GT28F640C3TC100 (NUMONYX) PDF技术资料下载 GT28F640C3TC100 供应信息 IC Datasheet 数据表 (6/70 页)-芯三七

28F800C3, 28F160C3, 28F320C3, 28F640C3

1.0

Introduction

This document contains the specifications for the 3 Volt Advanced+ Boot Block flash memory

family. These flash memories add features which can be used to enhance the security of systems:

instant block locking and a protection register.

Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except

where noted otherwise) and “V_PP= 12 V” refers to 12 V ±5%. Section 1.0 and Section 2.0 provide

an overview of the flash memory family including applications, pinouts, pin descriptions and

memory organization. Section 3.0 describes the operation of these products, with Section 4.0

providing the operating specifications. Ordering information is outlined in Section 5.0, and

additional reference material is located in Section 6.0.

The 3 Volt Advanced+ Boot Block flash memory features:

• Zero-latency, flexible block locking

• 128-bit Protection Register

• Simple system implementation for 12 V production programming with 2.7 V in-field

programming

• Ultra-low power operation at 2.7 V

• Minimum 100,000 block erase cycles

• Common Flash Interface for software query of device specs and features

Table 1. 3 Volt Advanced+ Boot Block Feature Summary

Feature

8 Mbit⁽¹⁾, 16 Mbit, 32 Mbit⁽²⁾

Reference

Table 8

V

Operating Voltage

Voltage

2.7 V – 3.6 V⁽³⁾

CC

Provides complete write protection with optional 12 V Fast Programming

Table 8

PP

I/O Voltage

2.7 V– 3.6 V

16-bit

CCQ

Bus Width

Table 2

8 Mbit: 90, 110 @ 2.7 V and 80, 100 @ 3.0 V

16 Mbit: 70, 80, 90, 110 @ 2.7 V and 70, 80, 100 @ 3.0 V

32 Mbit: 70, 90, 100, 110 @ 2.7 V and 70, 90, 100 @ 3.0 V

Speed (ns)

Section 4.4

64 Mbit: 90, 100 @ 2.7 V and 90, 100 @ 3.0 V

8 x 4-Kword parameter

8-Mb: 15 x 32-Kword main

16-Mb: 31 x 32-Kword main

32-Mb: 63 x 32-Kword main

64-Mb: 127 x 32-Kword main

Appendix 2.2

Appendix E

Blocking (top or bottom)

Operating Temperature

Program/Erase Cycling

Extended: –40 °C to +85 °C

100,000 cycles

Table 8

48-Lead TSOP

Packages

Figure 1, 2 and 3

48-Ball µBGA* CSP ⁽¹⁾, 48-Ball VF BGA, Easy BGA

Block Locking

Flexible locking of any block with zero latency

Section 3.3

Section 3.4

Protection Register

64-bit unique device number, 64-bit user programmable

NOTES:

1. 8-Mbit density not available in µBGA* CSP.

2. See Specification Update for changes to 32-Mbit devices (order 297938).

3. V Max = 3.3 V on 0.25µm 32-Mbit devices.

CC

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1.1

Product Overview

Intel provides secure low voltage memory solutions with the Advanced Boot Block family of

products. A new block locking feature allows instant locking/unlocking of any block with zero-

latency. A 128-bit protection register allows unique flash device identification.

Discrete supply pins provide single voltage read, program, and erase capability at 2.7 V while also

allowing 12 V V_PPfor faster production programming. Improved 12 V, a new feature designed to

reduce external logic, simplifies board designs when combining 12 V production programming

with 2.7 V in-field programming.

The 3 Volt Advanced+ Boot Block flash memory products are available in x16 packages in the

following densities: (see Section 5.0, “Ordering Information” on page 40)

• 8-Mbit (8,388,608 bit) flash memories organized as 512 Kwords of 16 bits each

• 16-Mbit (16,777,216 bit) flash memories organized as 1024 Kwords of 16 bits each

• 32-Mbit (33,554,432 bit) flash memories organized as 2048 Kwords of 16 bits each

• 64-Mbit (67,108,864 bit) flash memories organized as 4096 Kwords of 16 bits each

Eight 4-Kword parameter blocks are located at either the top (denoted by -T suffix) or the bottom

(-B suffix) of the address map in order to accommodate different microprocessor protocols for

kernel code location. The remaining memory is grouped into 64-Kbyte main blocks (see Appendix

E).

All blocks can be locked or unlocked instantly to provide complete protection for code or data (see

Section 3.3, “Flexible Block Locking” on page 15 for details).

The Command User Interface (CUI) serves as the interface between the microprocessor or

microcontroller and the internal operation of the flash memory. The internal Write State Machine

(WSM) automatically executes the algorithms and timings necessary for program and erase

operations, including verification, thereby unburdening the microprocessor or microcontroller. The

status register indicates the status of the WSM by signifying block erase or word program

completion and status.

Program and erase automation allows program and erase operations to be executed using an

industry-standard two-write command sequence to the CUI. Program operations are performed in

word increments. Erase operations erase all locations within a block simultaneously. Both program

and erase operations can be suspended by the system software in order to read from any other

block. In addition, data can be programmed to another block during an erase suspend.

The 3 Volt Advanced+ Boot Block flash memories offer two low power savings features:

Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode

following the completion of a read cycle. Standby mode is initiated when the system deselects the

device by driving CE# inactive. Combined, these two power savings features significantly reduce

power consumption.

The device can be reset by lowering RP# to GND. This provides CPU-memory reset

synchronization and additional protection against bus noise that may occur during system reset and

power-up/down sequences (see Section 3.5 and Section 3.6).

Refer to Section 4.4, “DC Characteristics” on page 25 for complete current and voltage

specifications. Refer to Section 4.5 and Section 4.6 for read and write performance specifications.

Program and erase times and shown in Section 4.7.

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2.0

Product Description

This section provides device pin descriptions and package pinouts for the 3 Volt Advanced+ Boot

Block flash memory family, which is available in 48-lead TSOP (x16) and 48-ball µBGA and Easy

BGA packages (Figures 1, 2 and 3, respectively).

2.1

Package Pinouts

Figure 1. 48-Lead TSOP Package

A₁₅

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A₁₆

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

A₉

V_CCQ

GND

DQ₁₅

DQ₇

DQ₁₄

DQ₆

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

DQ₁₁

DQ₃

DQ₁₀

DQ₂

DQ₉

DQ₁

DQ₈

DQ₀

OE#

GND

CE#

A₀

A₈

64 M

32 M

A₂₁

A₂₀

WE#

RP#

V_PP

WP#

A₁₉

A₁₈

A₁₇

A₇

A₆

A₅

A₄

A₃

A₂

A₁

Advanced+ Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

16 M

0645_02

NOTE: Lower densities will have NC on the upper address pins. For example, a 16-Mbit device will have NC on

Pins 9 and 10.

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Figure 2. 48-Ball µBGA* and 48-Ball Very Thin Profile Fine Pitch BGA Chip Size Package

(Top View, Ball Down)

1

2

3

4

5

6

7

8

16M

A

B

C

D

E

F

A₁₃

A₁₁

A₈

V_PP

WP#

A₁₉

A₇

A₄

A₁₄

A₁₀

WE#

A₉

RP#

A₂₁

A₁₈

A₁₇

A₅

A₃

A₂

A₁

32M

64M

A₁₅

A₁₂

A₂₀

A₆

A₁₆

D₁₄

D₁₅

D₇

D₅

D₆

D₁₁

D₁₂

D₄

D₂

D₃

D₈

D₉

CE#

D₀

A₀

V_CCQ

GND

OE#

D₁₃

V_CC

D₁₀

D₁

NOTES:

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the

upper address solder balls. Routing is not recommended in this area. A₁₉is the upgrade address for the

16-Mbit device. A₂₀is the upgrade address for the 32-Mbit device. A₂₁is the upgrade address for the 64-Mbit

device.

2. 8-Mbit not available on µBGA* CSP.

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Figure 3. 8 x 8 Easy BGA Package

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

A

B

C

A₁

A₂

A₃

A₄

A₆

A₁₈V_PPV_CCGND A₁₀

A₁₅

A₁₄

A₁₃

A₉

A₁₅

A₁₄

A₁₃

A₉

A₁₀GND V_CCV_PPA₁₈

A₆

A₁

A₂

A₃

A₄

(1)

A₁₇A₁₉

RP# DU A₂₀

A₁₁

A₁₂

A₈

A₁₁A₂₀

DU RP# A₁₉

A₁₇

(1)

A₇WP# WE# DU A₂₁

A₁₂A₂₁

DU WE# WP# A₇

D

A₅DU DU DU DU

A₈DU DU

DU DU

A₅

E

F

E

F

DQ₈DQ₁DQ₉DQ₃DQ₁₂DQ₆DU DU

CE# DQ₀DQ₁₀DQ₁₁DQ₅DQ₁₄DU DU

DU DU DQ₆DQ₁₂DQ₃DQ₉DQ₁DQ₈

DU DU DQ₁₄DQ₅DQ₁₁DQ₁₀

CE#

DQ₀

G

H

G

H

A₀V_SSQDQ₂DQ₄DQ₁₃DQ₁₅GND A₁₆

A₁₆GND D₁₅D₁₃DQ₄DQ₂V_SSQA₀

(2)

A₂₂OE# V_CCQV_CCV_SSQDQ₇V_CCQ

DU

DU V_CCQD₇V_SSQV_CCV_CCQOE# A₂₂

Top View - Ball Side Down

Bottom View - Ball Side Up

16fast

NOTES:

1. A denotes 16 Mbit; A denotes 32 Mbit; A denotes 64 Mbit.

19

20

21

2. A indicates future density upgrade path to128 Mbit (not yet available).

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Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions

Symbol

Type

Name and Function

ADDRESS INPUTS: Memory addresses are internally latched during a program or erase cycle.

A –A

INPUT

0

21

8-Mbit: A[0-18], 16-Mbit: A[0-19], 32-Mbit: A[0-20], 64-Mbit: A[0-21]

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Inputs commands to the Command User Interface when CE# and WE# are active.

Data is internally latched. Outputs array, configuration and status register data. The data pins float

to tri-state when the chip is de-selected or the outputs are disabled.

INPUT/

OUTPUT

DQ –DQ

0

7

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Data is internally latched. Outputs array and configuration data. The data pins float to

tri-state when the chip is de-selected.

INPUT/

OUTPUT

DQ –DQ

8

15

CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers.

CE# is active low. CE# high de-selects the memory device and reduces power consumption to

standby levels.

CE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read

operation. OE# is active low.

OE#

WE#

INPUT

WRITE ENABLE: Controls writes to the command register and memory array. WE# is active low.

Addresses and data are latched on the rising edge of the second WE# pulse.

RESET/DEEP POWER-DOWN: Uses two voltage levels (V , V ) to control reset/deep power-

IL

IH

down mode.

When RP# is at logic low, the device is in reset/deep power-down mode, which drives the

outputs to High-Z, resets the Write State Machine, and minimizes current levels (I ).

RP#

INPUT

CCD

When RP# is at logic high, the device is in standard operation. When RP# transitions from

logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.

WRITE PROTECT: Controls the lock-down function of the flexible Locking feature.

When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down

cannot be unlocked through software.

WP#

When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-

down are now locked and can be unlocked and locked through software. After WP# goes low, any

blocks previously marked lock-down revert to that state.

See Section 3.3 for details on block locking.

V

SUPPLY

INPUT

DEVICE POWER SUPPLY: [2.7 V–3.6 V] Supplies power for device operations.

I/O POWER SUPPLY: Supplies power for input/output buffers.

CC

CCQ

[2.7 V–3.6 V] This input should be tied directly to V

.

CC

PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.6 V or 11.4 V–12.6 V] Operates as a input at

logic levels to control complete device protection. Supplies power for accelerated program and

erase operations in 12 V ± 5% range. This pin cannot be left floating.

Lower V ≤ V

, to protect all contents against Program and Erase commands.

PP

PPLK

Set V = V for in-system read, program and erase operations. In this configuration, V

PP

CC

INPUT/

SUPPLY

can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note that if

is driven by a logic signal, V 1.65. That is, V must remain above 1.65 V to perform in-

V

PP

V

PP

IH =

PP

system flash modifications.

Raise V to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V

PP

± 5% to V can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles

PP

on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum. See

PP

Section 3.4 for details on V voltage configurations.

PP

GND

NC

SUPPLY

GROUND: For all internal circuitry. All ground inputs must be connected.

NO CONNECT: Pin may be driven or left floating.

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2.2

Block Organization

The 3 Volt Advanced+ Boot Block is an asymmetrically-blocked architecture that enables system

integration of code and data within a single flash device. Each block can be erased independently

of the others up to 100,000 times. For the address locations of each block, see the memory maps in

Appendix E.

2.2.1

2.2.2

Parameter Blocks

The 3 Volt Advanced+ Boot Block flash memory architecture includes parameter blocks to

facilitate storage of frequently updated small parameters (i.e., data that would normally be stored in

an EEPROM). Each device contains eight parameter blocks of 4 Kwords (4,096 words).

Main Blocks

After the parameter blocks, the remainder of the array is divided into 32-Kword (32,768 words)

main blocks for data or code storage. Each 8-Mbit, 16-Mbit, 32-Mbit, or 64-Mbit device contains

15, 31, 63, or 127 main blocks, respectively.

3.0

Principles of Operation

The 3 Volt Advanced+ Boot Block flash memory family utilizes a CUI and automated algorithms

to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs

and fixed power supplies during erasure and programming.

The internal WSM completely automates program and erase operations while the CUI signals the

start of an operation and the status register reports status. The CUI handles the WE# interface to the

data and address latches, as well as system status requests during WSM operation.

3.1

Bus Operation

The 3 Volt Advanced+ Boot Block flash memory devices read, program and erase in-system via

the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard

microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash

component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3 on page 8.

3.1.1

Read

The flash memory has four read modes available: read array, read configuration, read status and

read query. These modes are accessible independent of the V_PPvoltage. The appropriate read mode

command must be issued to the CUI to enter the corresponding mode. Upon initial device power-

up or after exit from reset, the device automatically defaults to read array mode.

CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection

control; when active it enables the flash memory device. OE# is the data output control and it

drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at

V_IH. Figure 8, “AC Waveform: Read Operations” on page 32 illustrates a read cycle.

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3.1.2

3.1.3

Output Disable

With OE# at a logic-high level (V_IH), the device outputs are disabled. Output pins are placed in a

high-impedance state.

Standby

Deselecting the device by bringing CE# to a logic-high level (V_IH) places the device in standby

mode, which substantially reduces device power consumption without any latency for subsequent

read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If

deselected during program or erase operation, the device continues to consume active power until

the program or erase operation is complete.

Table 3. Bus Operations

Mode

Notes

RP#

CE#

OE#

WE#

DQ

0–7

8–15

Read (Array, Status, Configuration, or Query)

1, 2,3

1

V

D

IH

IL

IH

IL

IH

OUT

Output Disable

Standby

Reset

V

High Z

IH

1

V

X

1,4

V

X

IL

Write

1,4,5,6

V

D

IN

IH

IL

IH

IL

IN

NOTES:

1. X must be V_IL, V_IHfor control pins and addresses.

2. See DC Characteristics for V_PPLK, V_PP1, V_PP2, V_PP3, voltages.

3. Manufacturer and device codes may also be accessed in read configuration mode (A_1–A₂₀= 0). See Table 4

on page 10.

4. To program or erase the lockable blocks, hold WP# at V_IH.

5. Refer to Table 5 on page 13 for valid D_INduring a write operation.

6. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

8-bit devices use only DQ [0:7], 16-bit devices use DQ [0:15].

3.1.4

Reset

From read mode, RP# at V_ILfor time t_PLPHdeselects the memory, places output drivers in a high-

impedance state, and turns off all internal circuits. After return from reset, a time t_PHQVis required

until the initial read access outputs are valid. A delay (t_PHWLor t_PHEL) is required after return from

reset before a write can be initiated. After this wake-up interval, normal operation is restored. The

CUI resets to read array mode, the status register is set to 80H, and all blocks are locked. This case

is shown in Figure 10, “AC Waveform: Reset Operations” on page 39 (section A).

If RP# is taken low for time t_PLPHduring a program or erase operation, the operation will be

aborted and the memory contents at the aborted location (for a program) or block (for an erase) are

no longer valid, since the data may be partially erased or written. The abort process goes through

the following sequence: When RP# goes low, the device shuts down the operation in progress, a

process which takes time t_PLRHto complete. After this time t_PLRH, the part will either reset to read

array mode (if RP# has gone high during t_PLRH, Figure 10, section B) or enter reset mode (if RP# is

still logic low after t_PLRH, Figure 10, section C). In both cases, after returning from an aborted

operation, the relevant time t_PHQVor t_PHWL/t_PHELmust be observed before a read or write

operation is initiated, as discussed in the previous paragraph. However, in this case, these delays

are referenced to the end of t_PLRHrather than when RP# goes high.

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Similar to any automated device, it is important to assert RP# during system reset. When the

system comes out of reset, the processor expects to read from the flash memory. Automated flash

memories provide status information when read during program or block erase operations. If a

CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the

flash memory may be providing status information instead of array data. Intel^®Flash memories

allow proper CPU initialization following a system reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.1.5

Write

A write takes place when both CE# and WE# are low and OE# is high. Commands are written to

the Command User Interface (CUI) using standard microprocessor write timings to control flash

operations. The CUI does not occupy an addressable memory location. The address and data buses

are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. See Figure

9, “AC Waveform: Program and Erase Operations” on page 38. The available commands are

shown in Table 6 on page 14, and Appendix A provides detailed information on moving between

the different modes of operation using CUI commands.

There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of

these commands to the internal Command User Interface (CUI) initiates a sequence of internally-

timed functions that culminate in the completion of the requested task (unless that operation is

aborted by either RP# being driven to V_ILfor t_PLRHor an appropriate suspend command).

3.2

Modes of Operation

The flash memory has four read modes and two write modes. The read modes are read array, read

configuration, read status, and read query. The write modes are program and erase. Three

additional modes (erase suspend to program, erase suspend to read and program suspend to read)

are available only during suspended operations. These modes are reached using the commands

summarized in Tables 5 and 6. For a comprehensive chart showing the state transitions, see

Appendix A.

3.2.1

Read Array

When RP# transitions from V_IL(reset) to V_IH, the device defaults to read array mode and will

respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI

commands.

When the device is in read array mode, four control signals control data output:

• WE# must be logic high (V_IH)

• CE# must be logic low (V_IL)

• OE# must be logic low (V_IL)

• RP# must be logic high (V_IH)

In addition, the address of the desired location must be applied to the address pins. If the device is

not in read array mode, as would be the case after a program or erase operation, the Read Array

command (FFH) must be written to the CUI before array reads can take place.

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3.2.2

Read Configuration

The Read Configuration mode outputs three types of information: the manufacturer/device

identifier, the block locking status, and the protection register. The device is switched to this mode

by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses

shown in Table 4 retrieve the specified information. To return to read array mode, write the Read

Array command (FFH).

Table 4. Read Configuration Table

Item

Address

Data

Manufacturer Code (x16)

Device ID (See Appendix F)

Block Lock Configuration⁽¹⁾

• Block Is Unlocked

00000

00001

0089

ID

XX002⁽²⁾

LOCK

DQ = 0

0

• Block Is Locked

DQ = 1

0

• Block Is Locked-Down

Protection Register Lock⁽³⁾

Protection Register (x16)

DQ = 1

1

80

PR-LK

81–88

PR

NOTES:

1. See Section 3.3.4 for valid lock status outputs.

2. “XX” specifies the block address of lock configuration being read.

3. See Section 3.4 for protection register information.

4. Other locations within the configuration address space are reserved by Intel for future use.

3.2.3

Read Status Register

The status register indicates the status of device operations, and the success/failure of that

operation. The Read Status Register (70H) command causes subsequent reads to output data from

the status register until another command is issued. To return to reading from the array, issue a

Read Array (FFH) command.

The status register bits are output on DQ₀–DQ₇. The upper byte, DQ₈–DQ₁₅, outputs 00H during a

Read Status Register command.

The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs

last. This prevents possible bus errors which might occur if status register contents change while

being read. CE# or OE# must be toggled with each subsequent status read, or the status register

will not indicate completion of a program or erase operation.

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status

register indicate whether the WSM was successful in performing the desired operation (see

Table 7, “Status Register Bit Definition” on page 15).

3.2.3.1

Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear

status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these

bits can only be cleared through the use of the Clear Status Register (50H) command. By allowing

the system software to control the resetting of these bits, several operations may be performed

(such as cumulatively programming several addresses or erasing multiple blocks in sequence)

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before reading the status register to determine if an error occurred during that series. Clear the

status register before beginning another command or sequence. Note that this is different from a

burst device. The Read Array command must be issued before data can be read from the memory

array. Resetting the device also clears the status register.

3.2.4

3.2.5

Read Query

The read query mode outputs Common Flash Interface (CFI) data when the device is read. This can

be accessed by writing the Read Query Command (98H). The CFI data structure contains

information such as block size, density, command set and electrical specifications. Once in this

mode, read cycles from addresses shown in Appendix C retrieve the specified information. To

return to read array mode, write the Read Array command (FFH).

Program Mode

Programming is executed using a two-write sequence. The Program Setup command (40H) is

written to the CUI followed by a second write which specifies the address and data to be

programmed. The WSM will execute a sequence of internally timed events to program desired bits

of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If the user

attempts to program “1”s, the memory cell contents do not change and no error occurs.

The status register indicates programming status: while the program sequence executes, status bit 7

is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the

only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the program status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If

SR.3 is set then V_PPwas not within acceptable limits, and the WSM did not execute the program

command. If SR.1 is set, a program operation was attempted on a locked block and the operation

was aborted.

The status register should be cleared before attempting the next operation. Any CUI instruction can

follow after programming is completed; however, to prevent inadvertent status register reads, be

sure to reset the CUI to read array mode.

3.2.5.1

Suspending and Resuming Program

The Program Suspend command halts an in-progress program operation so that data can be read

from other locations of memory. Once the programming process starts, writing the Program

Suspend command to the CUI requests that the WSM suspend the program sequence (at

predetermined points in the program algorithm). The device continues to output status register data

after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will

determine when the program operation has been suspended (both will be set to “1”). t_WHRH1

/

t_EHRH1specify the program suspend latency.

A Read Array command can now be written to the CUI to read data from blocks other than that

which is suspended. The only other valid commands while program is suspended are Read Status

Register, Read Configuration, Read Query, and Program Resume. After the Program Resume

command is written to the flash memory, the WSM will continue with the programming process

and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically

outputs status register data when read (see Figure 12, “Program Suspend/Resume Flowchart” on

page 45) after the Program Resume command is written. V_PPmust remain at the same V_PPlevel

used for program while in program suspend mode. RP# must also remain at V_IH.

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3.2.6

Erase Mode

To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an

address identifying the block to be erased. This address is latched internally when the Erase

Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only

one block can be erased at a time. The WSM will execute a sequence of internally timed events to

program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all

bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

When the status register indicates that erasure is complete, check the erase status bit to verify that

the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status

register will be set to a “1,” indicating an erase failure. If V_PPwas not within acceptable limits after

the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,

SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that

V

_PPsupply voltage was not within acceptable limits.

After an erase operation, clear the status register (50H) before attempting the next operation. Any

CUI instruction can follow after erasure is completed; however, to prevent inadvertent status

register reads, it is advisable to place the flash in read array mode after the erase is complete.

3.2.6.1

Suspending and Resuming Erase

Since an erase operation requires on the order of seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in order to read data from or program data to

another block in memory. Once the erase sequence is started, writing the Erase Suspend command

to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status

register will indicate if/when the erase operation has been suspended. Erase suspend latency is

specified by t_WHRH2/t_EHRH2

.

A Read Array/Program command can now be written to the CUI to read/program data from/to

blocks other than that which is suspended. This nested Program command can subsequently be

suspended to read yet another location. The only valid commands while erase is suspended are

Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase

Resume, Lock Block, Unlock Block and Lock-Down Block. During erase suspend mode, the chip

can be placed in a pseudo-standby mode by taking CE# to V_IH. This reduces active current

consumption.

Erase Resume continues the erase sequence when CE# = V_IL. Similar to the end of a standard erase

operation, the status register must be read and cleared before the next instruction is issued.

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Table 5. Command Bus Operations

First Bus Cycle

Second Bus Cycle

Command

Notes

Oper

Addr

Data

Oper

Addr

Data

Read Array

1

1, 2

1

Write

X

FFH

90H

Read Configuration

Read Query

Read

IA

QA

X

ID

98H

QD

Read Status Register

Clear Status Register

Program

70H

SRD

1

50H

1, 3

1

40H/10H

20H

Write

PA

BA

PD

Block Erase/Confirm

Program/Erase Suspend

Program/Erase Resume

Lock Block

D0H

1

B0H

D0H

60H

1

Write

BA

PA

01H

D0H

2FH

PD

Unlock Block

1

60H

Lock-Down Block

Protection Program

1

60H

1

C0H

X = Don’t Care

PA = Prog Addr

PD = Prog Data

BA = Block Addr

IA = Identifier Addr. QA = Query Addr.

ID = Identifier Data QD = Query Data

SRD = Status Reg.

Data

NOTES:

1. Following the Read Configuration or Read Query commands, read operations output device configuration or

CFI query information, respectively. See Section 3.2.2 and Section 3.2.4.

2. Either 40H or 10H command is valid, but the Intel standard is 40H.

3. When writing commands, the upper data bus [DQ_8–DQ₁₅] should be either V_ILor V_IH, to minimize current

draw.

Bus operations are defined in Table 3, “Bus Operations” on page 8.

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Table 6. Command Codes and Descriptions

Code

Device Mode

Description

FF

Read Array

This command places the device in read array mode which outputs array data on the data pins.

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The

second cycle latches addresses and data information and initiates the WSM to execute the

Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read

Array command is required after programming to read array data. See Section 3.2.5.

40

20

Program Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an Erase

Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”

(b) place the device into the read status register mode, and (c) wait for another command. See

Section 3.2.6.

Erase Set-Up

If the previous command was an Erase Set-Up command, then the CUI will close the address

and data latches and begin erasing the block indicated on the address pins. During program/

erase, the device will respond only to the Read Status Register, Program Suspend and Erase

Suspend commands and will output status register data when CE# or OE# is toggled.

Erase Confirm

D0

Program/Erase

Resume

If a program or erase operation was previously suspended, this command will resume that

operation.

If the previous command was Configuration Set-Up, the CUI will latch the address and unlock

the block indicated on the address pins. If the block had been previously set to Lock-Down, this

operation will have no effect. (Section 3.3)

Unlock Block

Issuing this command will begin to suspend the currently executing program/erase operation.

The status register will indicate when the operation has been successfully suspended by

setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit

(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the

state of all input control pins except RP#, which will immediately shut down the WSM and the

Program

Suspend

B0

70

Erase

Suspend

remainder of the chip if RP# is driven to V . See Sections 3.2.5.1 and 3.2.6.1.

IL

This command places the device into read status register mode. Reading the device will output

the contents of the status register, regardless of the address presented to the device. The

device automatically enters this mode after a program or erase operation has been initiated.

See Section 3.2.3.

Read Status

Register

The WSM can set the block lock status (SR.1) , V Status (SR.3), program status (SR.4), and

erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this

command clears those bits to “0.”

PP

Clear Status

Register

50

90

Read

Configuration

Puts the device into the read configuration mode so that reading the device will output the

manufacturer/device codes or block lock status. Section 3.2.2.

Prepares the CUI for changes to the device configuration, such as block locking changes. If the

next command is not Block Unlock, Block Lock, or Block Lock-Down, then the CUI will set both

the program and erase status register bits to indicate a command sequence error. See Section

3.2.

Configuration

Set-Up

60

If the previous command was Configuration Set-Up, the CUI will latch the address and lock the

block indicated on the address pins. (Section 3.3)

01

2F

98

Lock-Block

Lock-Down

If the previous command was a Configuration Set-Up command, the CUI will latch the address

and lock-down the block indicated on the address pins. (Section 3.3)

Read

Query

Puts the device into the read query mode so that reading the device will output Common Flash

Interface information. See Section 3.2.4 and Appendix C.

This is a two-cycle command. The first cycle prepares the CUI for a program operation to the

protection register. The second cycle latches addresses and data information and initiates the

WSM to execute the Protection Program algorithm to the protection register. The flash outputs

status register data when CE# or OE# is toggled. A Read Array command is required after

programming to read array data. See Section 3.4.

Protection

Program

Setup

C0

10

00

Alt. Prog Set-Up

Operates the same as Program Set-up command. (See 40H/Program Set-Up)

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine these

codes for future functions.

NOTE: See Appendix A for mode transition information.

14

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Table 7. Status Register Bit Definition

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

PSS

2

BLS

1

R

0

NOTES:

SR.7 WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

Check Write State Machine bit first to determine Word Program

or Block Erase completion, before checking Program or Erase

Status bits.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to “1.” ESS bit remains set to “1” until

an Erase Resume command is issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erase

0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the max. number

of erase pulses to the block and is still unable to verify

successful block erasure.

SR.4 = PROGRAM STATUS (PS)

1 = Error in Programming

0 = Successful Programming

When this bit is set to “1,” WSM has attempted but failed to

program a word/byte.

The V status bit does not provide continuous indication of

PP

V

level. The WSM interrogates V level only after the

PP

SR.3 = V STATUS (VPPS)

Program or Erase command sequences have been entered,

and informs the system if V has not been switched on. The

PP

1 = V Low Detect, Operation Abort

PP

0 = V OK

V

is also checked before the operation is verified by the

PP

WSM. The V status bit is not guaranteed to report accurate

PP

feedback between V

and V

Min.

PPLK

PP1

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

When Program Suspend is issued, WSM halts execution and

sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”

until a Program Resume command is issued.

SR.1 = BLOCK LOCK STATUS

1 = Prog/Erase attempted on a locked

block; Operation aborted.

If a program or erase operation is attempted to one of the

locked blocks, this bit is set by the WSM. The operation

specified is aborted and the device is returned to read status

mode.

0 = No operation to locked blocks

This bit is reserved for future use and should be masked out

when polling the status register.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.

3.3

Flexible Block Locking

Intel 3 Volt Advanced+ Boot Block products offer an instant, individual block locking scheme that

allows any block to be locked or unlocked with no latency, enabling instant code and data

protection.

This locking scheme offers two levels of protection. The first level allows software-only control of

block locking (useful for data blocks that change frequently), while the second level requires

hardware interaction before locking can be changed (useful for code blocks that change

infrequently).

The following sections will discuss the operation of the locking system. The term “state [XYZ]”

will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ₁of

the Block Lock status register, and Z = bit DQ₀of the Block Lock status register. Table 9, “Block

Locking State Transitions” on page 18 defines all of these possible locking states.

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3.3.1

Locking Operation

The following concisely summarizes the locking functionality.

• All blocks power-up locked, then can be unlocked or locked with the Unlock and Lock

commands.

• The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0.

— When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down

blocks.

— When WP# returns to 0, locked-down blocks return to Lock-Down.

— Lock-Down is cleared only when the device is reset or powered-down.

The locking status of each block can be set to Locked, Unlocked, and Lock-Down, each of which

will be described in the following sections. A comprehensive state table for the locking functions is

shown in Table 9 on page 18, and a flowchart for locking operations is shown in Figure 15 on

page 48.

3.3.1.1

Locked State

The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked

blocks are fully protected from alteration. Any program or erase operations attempted on a locked

block will return an error on bit SR.1 of the status register. The status of a locked block can be

changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked

block can be locked by writing the Lock command sequence, 60H followed by 01H.

3.3.2

3.3.3

Unlocked State

Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks

return to the Locked state when the device is reset or powered down. The status of an unlocked

block can be changed to Locked or Locked-Down using the appropriate software commands. A

Locked block can be unlocked by writing the Unlock command sequence, 60H followed by D0H.

Lock-Down State

Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just

like Locked blocks), but their protection status cannot be changed using software commands alone.

A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence,

60H followed by 2FH. Locked-Down blocks revert to the Locked state when the device is reset or

powered down.

The Lock-Down function is dependent on the WP# input pin. When WP# = 0, blocks in Lock-

Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-

Down function is disabled ([111]) and locked-down blocks can be individually unlocked by

software command to the [110] state, where they can be erased and programmed. These blocks can

then be relocked [111] and unlocked [110] as desired while WP# remains high. When WP# goes

low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of

any changes made while WP# was high. Device reset or power-down resets all blocks, including

those in Lock-Down, to Locked state.

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3.3.4

Reading a Block’s Lock Status

The lock status of every block can be read in the configuration read mode of the device. To enter

this mode, write 90H to the device. Subsequent reads at Block Address + 00002 will output the

lock status of that block. The lock status is represented by DQ₀and DQ₁. DQ₀indicates the Block

Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also

automatically set when entering Lock-Down. DQ₁indicates Lock-Down status and is set by the

Lock-Down command. It cannot be cleared by software, only by device reset or power-down.

Table 8. Block Lock Status

Item

Address

Data

Block Lock Configuration

• Block Is Unlocked

• Block Is Locked

XX002

LOCK

DQ = 0

0

DQ = 1

0

• Block Is Locked-Down

DQ = 1

1

3.3.5

Locking Operations during Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard

locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when

another block needs to be updated while an erase operation is in progress.

To change block locking during an erase operation, first write the erase suspend command (B0H),

then check the status register until it indicates that the erase operation has been suspended. Next

write the desired lock command sequence to a block and the lock status will be changed. After

completing any desired lock, read, or program operations, resume the erase operation with the

Erase Resume command (D0H).

If a block is locked or locked-down during a suspended erase of the same block, the locking status

bits will be changed immediately, but when the erase is resumed, the erase operation will complete.

Locking operations cannot be performed during a program suspend. Refer to Appendix A for

detailed information on which commands are valid during erase suspend.

3.3.6

Status Register Error Checking

Using nested locking or program command sequences during erase suspend can introduce

ambiguity into status register results.

Since locking changes are performed using a two cycle command sequence, e.g., 60H followed by

01H to lock a block, following the Configuration Setup command (60H) with an invalid command

will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock

command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1 and will remain at 1

after the erase is resumed. When erase is complete, any possible error during the erase cannot be

detected via the status register because of the previous locking command error.

A similar situation happens if an error occurs during a program operation error nested within an

erase suspend.

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Table 9. Block Locking State Transitions

Current State

Lock Command Input Result (Next State)

Erase/Prog

Allowed?

X

Y

Z

Lock

Unlock

Lock-Down

WP#

DQ

Name

1

0

1

0

1

0

1

0

1

0

1

0

1

“Unlocked”

“Locked” (Default)

“Locked-Down”

“Unlocked”

Yes

No

Goes To [001]

No Change

Goes To [101]

No Change

Goes To [111]

No Change

Goes To [000]

No Change

Goes To [011]

No Change

No

Yes

No

No Change

Goes To [111]

No Change

“Locked”

Goes To [100]

No Change

Lock-Down Disabled

Yes

No

Goes To [110]

NOTES:

1. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ₁, and Z = DQ₀.

The current locking state of a block is defined by the state of WP# and the two bits of the block lock status

(DQ₀, DQ₁). DQ₀indicates if a block is locked (1) or unlocked (0). DQ₁indicates if a block has been locked-

down (1) or not (0).

2. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the

recommended default.

3. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or

disabled (No) in that block’s current locking state.

4. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking

commands (Lock, Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean

that writing the command to a block in the current locking state would change it to [001].

3.4

128-Bit Protection Register

The 3 Volt Advanced+ Boot Block architecture includes a 128-bit protection register than can be

used to increase the security of a system design. For example, the number contained in the

protection register can be used to “mate” the flash component with other system components such

as the CPU or ASIC, preventing device substitution. Additional application information can be

found in Intel application note AP-657 Designing with the Advanced+ Boot Block Flash Memory

Architecture.

The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is

programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other

segment is left blank for customer designs to program as desired. Once the customer segment is

programmed, it can be locked to prevent reprogramming.

3.4.1

Reading the Protection Register

The protection register is read in the configuration read mode. The device is switched to this mode

by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses

shown in Appendix G retrieve the specified information. To return to read array mode, write the

Read Array command (FFH).

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3.4.2

Programming the Protection Register

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for

byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the

device will latch in address and data and program the specified location. The allowable addresses

are shown in Appendix G. See Figure 16, “Protection Register Programming Flowchart” on

page 49. Attempts to address Protection Program commands outside the defined protection register

address space should not be attempted. This space is reserved for future use. Attempting to

program to a previously locked protection register segment will result in a status register error

(program error bit SR.4 and lock error bit SR.1 will be set to 1).

3.4.3

Locking the Protection Register

The user-programmable segment of the protection register is lockable by programming Bit 1 of the

PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the

unique device number. This bit is set using the Protection Program command to program “FFFD”

to the PR-LOCK location. After these bits have been programmed, no further changes can be made

to the values stored in the protection register. Protection Program commands to a locked section

will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to

1). Protection register lockout state is not reversible.

Figure 4. Protection Register Memory Map

88H

4 Words

User Programmed

85H

84H

4 Words

Factory Programmed

81H

80H

PR Lock

0645_05

3.5

V

Program and Erase Voltages

PP

Intel 3 Volt Advanced+ Boot Block products provide in-system programming and erase in the

1.65 V–3.6 V range. For fast production programming, it also includes a low-cost, backward-

compatible 12 V programming feature.

3.5.1

Improved 12 Volt Production Programming

When V_PPis between 1.65 V and 3.6 V, all program and erase current is drawn through the V_CC

pin. Note that if V_PPis driven by a logic signal, V_IHmin = 1.65 V. That is, V_PPmust remain above

1.65 V to perform in-system flash modifications. When V_PPis connected to a 12 V power supply,

the device draws program and erase current directly from the V_PPpin. This eliminates the need for

an external switching transistor to control the voltage V_PP. Figure 5 on page 20 shows examples of

how the flash power supplies can be configured for various usage models.

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The 12 V V_PPmode enhances programming performance during the short period of time typically

found in manufacturing processes; however, it is not intended for extended use. 12 V may be

applied to V_PPduring program and erase operations for a maximum of 1000 cycles on the main

blocks and 2500 cycles on the parameter blocks. V_PPmay be connected to 12 V for a total of 80

hours maximum. Stressing the device beyond these limits may cause permanent damage.

3.5.2

V

≤ V

for Complete Protection

PP

PPLK

In addition to the flexible block locking, the V_PPprogramming voltage can be held low for absolute

hardware write protection of all blocks in the flash device. When V_PPis below V_PPLK, any

program or erase operation will result in a error, prompting the corresponding status register bit

(SR.3) to be set.

Figure 5. Example Power Supply Configurations

System Supply

V_CC

V_PP

V_CC

12 V Supply

V_PP

Prot#

(Logic Signal)

10

≤ KΩ

12 V Fast Programming

Low-Voltage Programming

Absolute Write Protection With V _PP

≤

V_PPLK

Absolute Write Protection via Logic Signal

System Supply

(Note 1)

System Supply

V_CC

V_PP

12 V Supply

Low Voltage and 12 V Fast Programming

Low-Voltage Programming

0645_06

NOTE:

1. A resistor can be used if the V supply can sink adequate current based on resistor value. See AP-657

CC

Designing with the Advanced+ Boot Block Flash Memory Architecture for details.

3.6

Power Consumption

Intel Flash devices have a tiered approach to power savings that can significantly reduce overall

system power consumption. The Automatic Power Savings (APS) feature reduces power

consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its

standby mode, where current consumption is even lower. The combination of these features can

minimize memory power consumption, and therefore, overall system power consumption.

3.6.1

Active Power (Program/Erase/Read)

With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer

to the DC Characteristic tables for I_CCcurrent values. Active power is the largest contributor to

overall system power consumption. Minimizing the active current could have a profound effect on

system power consumption, especially for battery-operated devices.

20

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3.6.2

3.6.3

Automatic Power Savings (APS)

Automatic Power Savings provides low-power operation during read mode. After data is read from

the memory array and the address lines are quiescent, APS circuitry places the device in a mode

where typical current is comparable to I_CCS. The flash stays in this static state with outputs valid

until a new location is read.

Standby Power

When CE# is at a logic-high level (V_IH) and the device is in read mode, the flash memory is in

standby mode, which disables much of the device’s circuitry and substantially reduces power

consumption. Outputs are placed in a high-impedance state independent of the status of the OE#

signal. If CE# transitions to a logic-high level during erase or program operations, the device will

continue to perform the operation and consume corresponding active power until the operation is

completed.

System engineers should analyze the breakdown of standby time versus active time and quantify

the respective power consumption in each mode for their specific application. This will provide a

more accurate measure of application-specific power and energy requirements.

3.6.4

Deep Power-Down Mode

The deep power-down mode is activated when RP# = V_IL(GND ± 0.2 V). During read modes,

RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery

from deep power-down requires a minimum time of t_PHQVfor read operations and t_PHWL/t_PHELfor

write operations.

During program or erase modes, RP# transitioning low will abort the in-progress operation. The

memory contents of the address being programmed or the block being erased are no longer valid as

the data integrity has been compromised by the abort. During deep power-down, all internal

circuits are switched to a low power savings mode (RP# transitioning to V_ILor turning off power to

the device clears the status register).

3.7

Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions.

Power supply sequencing is not required, since the device is indifferent as to which power supply,

V

_PPor V_CC, powers-up first.

3.7.1

RP# Connected to System Reset

The use of RP# during system reset is important with automated program/erase devices since the

system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs

without a flash memory reset, proper CPU initialization will not occur because the flash memory

may be providing status information instead of array data. Intel recommends connecting RP# to the

system CPU RESET# signal to allow proper CPU/flash initialization following system reset.

System designers must guard against spurious writes when V_CCvoltages are above V_LKO. Since

both WE# and CE# must be low for a command write, driving either signal to V_IHwill inhibit

writes to the device. The CUI architecture provides additional protection since alteration of

memory contents can only occur after successful completion of the two-step command sequences.

The device is also disabled until RP# is brought to V_IH, regardless of the state of its control inputs.

3UHOLPLQDU\

21

28F800C3, 28F160C3, 28F320C3, 28F640C3

By holding the device in reset (RP# connected to system PowerGood) during power-up/down,

invalid bus conditions during power-up can be masked, providing yet another level of memory

protection.

3.7.2

V

, V and RP# Transitions

CC PP

The CUI latches commands as issued by system software and is not altered by V_PPor CE#

transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after

V

_CCtransitions above V_LKO(Lockout voltage), is read array mode.

After any program or block erase operation is complete (even after V_PPtransitions down to

V

_PPLK), the CUI must be reset to read array mode via the Read Array command if access to the

flash memory array is desired.

3.8

Power Supply Decoupling

Flash memory’s power switching characteristics require careful device decoupling. System

designers should consider three supply current issues:

• Standby current levels (I_CCS

• Read current levels (I_CCR

)

• Transient peaks produced by falling and rising edges of CE#.

Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-

line control and proper decoupling capacitor selection will suppress these transient voltage peaks.

Each flash device should have a 0.1 µF ceramic capacitor connected between each V_CCand GND,

and between its V_PPand GND. These high- frequency, inherently low-inductance capacitors should

be placed as close as possible to the package leads.

22

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Parameter

Maximum Rating

Extended Operating Temperature

During Read

–40 °C to +85 °C

–65 °C to +125 °C

During Block Erase and Program

Temperature under Bias

Storage Temperature

Voltage On Any Pin (except V and V ) with Respect to GND

–0.5 V to +3.7 V⁽¹⁾

Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V^(1,2,3)

CC

PP

V

PP

CC

and V

Supply Voltage with Respect to GND

–0.2 V to +3.6 V

100 mA⁽⁴⁾

CCQ

Output Short Circuit Current

NOTES:

1. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V

for periods <20 ns. Maximum DC voltage on input/output pins is V +0.5 V which, during transitions, may

CC

overshoot to V +2.0 V for periods <20 ns.

CC

2. Maximum DC voltage on V may overshoot to +14.0 V for periods <20 ns.

PP

3. V Program voltage is normally 1.65 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a

PP

maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase.

V

may be connected to 12 V for a total of 80 hours maximum. See Section 3.5 for details.

PP

4. Output shorted for no more than one second. No more than one output shorted at a time.

NOTICE: This datasheet contains preliminary information on new products in production. Specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before

finalizing a design.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

3UHOLPLQDU\

23

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.2

Operating Conditions

Table 10. Temperature and Voltage Operating Conditions

Symbol

Parameter

Notes

Min

Max

Units

T

Operating Temperature

–40

2.7

+85

3.6

°C

A

V

Supply Voltage

1, 2

1

Volts

CC1

CC2

CCQ1

PP1

CC

3.0

3.6

I/O Supply Voltage

Supply Voltage

2.7

3.6

Volts

1

1.65

11.4

100,000

3.6

1, 3

3

12.6

Volts

PP2

Cycling

Block Erase Cycling

Cycles

NOTES:

1. V and V

must share the same supply when they are in the V

range.

CC

CCQ

CC1

2. V Max = 3.3 V for 0.25µm 32-Mbit devices.

CC

3. Applying V = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on

PP

the main blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of

PP

80 hours maximum. See Section 3.5 for details.

4.3

Capacitance

T_A= 25 °C, f = 1 MHz

Sym

Parameter

Notes

Typ

Max

Units

Conditions

= 0 V

C

Input Capacitance

Output Capacitance

1

6

8

pF

V

IN

OUT

10

12

V

= 0 V

OUT

NOTE:

1. Sampled, not 100% tested.

24

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.4

DC Characteristics

V

CC

2.7 V—3.6 V⁽²⁾

Sym

Parameter

V

Unit

Test Conditions

CCQ

Notes

Typ

Max

V

= V Max, V

= V

Max

CC

CCQ

I

Input Load Current

1,2

± 1

µA

LI

= V

or GND

CCQ

IN

V

= V Max, V

CC CCQ

CC

CCQ

I

Output Leakage Current

Standby Current for 0.18

1,2

1

0.2

7

± 10

15

LO

= V

or GND

CCQ

IN

V

= V Max, CE# = RP# = V

CC

V

CC

CCQ

CC

Micron Product

WP# = V

or GND

CCQ

I

CCS

V

= V Max, CE# = RP# = V

CC

V

Standby Current for 0.25

CC

1

10

7

25

Micron and 0.4 Micron Product

WP# = V

or GND

CCQ

V

= V Max, V

= V

Max

CCQ

V

Deep Power-Down Current

CC

CCQ

CC

1,2

15

for 0.18 Micron Product

= V

or GND, RP# = GND ± 0.2 V

CCQ

IN

I

CCD

V

Deep Power-Down Current

CC

V

= V Max, V

= V

Max

CCQ

CC

CCQ

for 0.25 Micron and 0.4 Micron

Product

1,2

7

9

25

18

µA

= V

or GND, RP# = GND ± 0.2 V

CCQ

IN

V

= V Max, V

= V

Max

CCQ

CC

CCQ

V

Read Current

1,2,3

1,4

mA

OE# = V , CE# = V , f = 5 MHz,

CCR

CC

IH

IL

I

= 0 mA, Inputs = V or V

OUT

IL IH

18

8

55

15

45

15

mA

V

= V

, Program in Progress

PP

PP1

PP2

PP1,

PP2

I

Program Current

CCW

(12 V), Program in Progress

Erase in Progress

16

8

V

Erase Current

1,4

CCE

CC

(12 V), Erase in Progress

Erase Suspend Current for

1,4,5

7

15

25

µA

CE# = V , Erase Suspend in Progress

IH

0.18 Micron Product

I

CCES

V

Erase Suspend Current for

CC

0.25 Micron and 0.4 Micron

Product

1,4,5

10

CE# = V , Erase Suspend in Progress

IH

CE# = V , Program

V

Program Suspend Current

IH

CC

7

15

25

µA

for 0.18 Micron Product

Suspend in Progress

I

CCWS

V

Program Suspend Current

CC

CE# = V , Program

IH

for 0.25 Micron and 0.4 Micron

Product

10

Suspend in Progress

I

V

Deep Power-Down Current

Standby Current

1

0.2

2

5

µA

RP# = GND ± 0.2 V, V ≤ V

PP CC

PPD

PP

5

V

≤ V

≥ V

PPS

PP

CC

1

±15

200

0.1

22

µA

I

V

Read Current

Program Current

Erase Current

PPR

PPW

PPE

PP

1,4

50

0.05

8

µA

CC

mA

=V

, Program in Progress

PP1

1,4

= V

(12 V), Program in Progress

, Program in Progress

PP2

PP1

PP2

0.05

8

0.1

22

(12 V), Program in Progress

3UHOLPLQDU\

25

28F800C3, 28F160C3, 28F320C3, 28F640C3

V

CC

2.7 V—3.6 V⁽²⁾

Sym

Parameter

V

Unit

Test Conditions

CCQ

Notes

Typ

Max

0.2

5

µA

V

= V

, Erase Suspend in Progress

(12 V),

PP

PP1

I

V

Erase Suspend Current

1,4

PPES

PP

PP2

50

0.2

50

200

5

Erase Suspend in Progress

V

= V

PP

PP1

µA

Program Suspend in Progress

Program Suspend Current

1,4

PPWS

PP

V

= V (12 V)

PP

PP2

200

Program Suspend in Progress

DC Characteristics, Continued

V

CC

2.7 V — 3.6 V

Sym

Parameter

V

Unit

Test Conditions

CCQ

Notes

Min

–0.4

Max

V

Input Low Voltage

V

*0.22 V

+0.3 V

V

IL

CC

V

Input High Voltage

2.0

IH

CCQ

V

= V Min

CC

V

Output Low Voltage

2

–0.10

0.10

V

= V

Min

CCQ

OL

CCQ

I

= 100 µA

OL

V

= V Min

CC

Output High Voltage

V

–0.1 V

= V

Min

CCQ

OH

CCQ

I

= –100 µA

OH

V

Lock-Out Voltage

6

1.0

3.6

V

Complete Write Protection

PPLK

PP1

PP

1.65

11.4

1.5

during Program / Erase

PP

Operations

6,7

12.6

PP2

V

Prog/Erase Lock Voltage

V

LKO

LKO2

CC

Prog/Erase Lock Voltage

1.2

CCQ

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V , T = +25 °C.

CC

A

2. The test conditions V Max, V

Max, V Min, and V

Min refer to the maximum or minimum V or

CC

CCQ

CC

CCQ CC

V

voltage listed at the top of each column. V Max = 3.3 V for 0.25µm 32-Mbit devices.

CCQ

CC

3. Automatic Power Savings (APS) reduces I

to approximately standby levels in static operation (CMOS

CCR

inputs).

4. Sampled, not 100% tested.

5. I

and I

are specified with device de-selected. If device is read while in erase suspend, current draw

CCES

CCWS

is sum of I

and I

. If the device is read while in program suspend, current draw is the sum of I

CCR CCWS

CCES

and I

.

CCR

6. Erase and Program are inhibited when V < V

and not guaranteed outside the valid V ranges of V

PP PP1

PP

PPLK

and V

.

PP2

7. Applying V = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the

PP

main blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours

PP

maximum. See Section 3.4 for details.

26

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 6. Input/Output Reference Waveform

V_CCQ

TEST POINTS

INPUT

OUTPUT

2

0.0

0645_07

Figure 7. Test Configuration

V_CCQ

R₁

Device

Under Test

Out

C_L

R₂

0645_08

Test Configuration

C (pF)

R (Ω)

2

L

1

2.7 V–3.6 V Standard Test

50

25K

NOTE: C includes jig capacitance.

L

3UHOLPLQDU\

27

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.5

AC Characteristics—Read Operations

Density

Product

8 Mbit

90 ns

3.0 V – 3.6 V 2.7 V – 3.6 V

110 ns

3.0 V – 3.6 V 2.7 V – 3.6 V

#

Sym

Parameter

Unit

V

CC

Note

Min

Max

Min

Max

Min

Max

Min

Max

R1

R2

R3

R4

R5

R6

R7

R8

R9

t

Read Cycle Time

80

90

100

110

ns

AVAV

Address to Output Delay

CE# to Output Delay

OE# to Output Delay

RP# to Output Delay

CE# to Output in Low Z

OE# to Output in Low Z

CE# to Output in High Z

OE# to Output in High Z

80

90

100

30

110

30

AVQV

ELQV

GLQV

PHQV

ELQX

GLQX

EHQZ

GHQZ

1

30

150

2

0

20

Output Hold from

Address, CE#, or OE#

Change, Whichever

Occurs First

R10

t

2

0

ns

OH

NOTES:

1. OE# may be delayed up to t

t

after the falling edge of CE# without impact on t

.

ELQV– GLQV

ELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 32.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

28

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Read Operations, continued

Density

Product

V_CC

16 Mbit

90 ns

70 ns

80 ns

110 ns

3.0 V–3.6 V 2.7 V–3.6 V

Para-

meter

#

Sym

Unit

2.7 V–3.6 V

3.0 V–3.6 V

2.7 V–3.6 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

R1

R2

t_AVAVRead Cycle Time

70

80

90

100

110

ns

Address to Output

t_AVQV

Delay

70

80

90

100

30

110

30

CE# to Output

t_ELQV

R3

R4

R5

R6

R7

R8

R9

ns

Delay⁽¹⁾

OE# to Output

t_GLQV

20

30

Delay⁽¹⁾

RP# to Output

t_PHQV

Delay

150

CE# to Output in

t_ELQX

0

Low Z⁽²⁾

OE# to Output in

t_GLQX

Low Z⁽²⁾

CE# to Output in

t_EHQZ

20

High Z⁽²⁾

OE# to Output in

t_GHQZ

High Z⁽²⁾

Output Hold from

Address, CE#, or

OE# Change,

Whichever Occurs

First⁽²⁾

R10

t_OH

0

ns

NOTES:

1. OE# may be delayed up to t

t

after the falling edge of CE# without impact on t

.

ELQV– GLQV

ELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 32.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

3UHOLPLQDU\

29

28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Read Operations, continued

Density

Product

32 Mbit

100 ns

Para-

meter

70 ns

90 ns

110 ns

#

Sym

Unit

V

2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2.7 V–3.3 V

Min Max Min Max Min Max Min Max Min Max Min Max

CC

Read Cycle Time

R1

t

70

90

100

110

ns

AVAV

Address to Output

Delay

R2

R3

t

70

90

100

110

ns

AVQV

CE# to Output

Delay⁽¹⁾

t

ELQV

OE# to Output

Delay⁽¹⁾

R4

R5

R6

t

20

30

ns

GLQV

t

RP# to Output Delay

150

PHQV

CE# to Output in

Low Z⁽²⁾

t

0

ELQX

GLQX

EHQZ

GHQZ

OE# to Output in

Low Z⁽²⁾

R7

R8

R9

t

ns

CE# to Output in

High Z⁽²⁾

20

OE# to Output in

High Z⁽²⁾

t

Output Hold from

Address, CE#, or

OE# Change,

Whichever Occurs

First⁽²⁾

R10

t

0

ns

OH

NOTES:

1. OE# may be delayed up to t

t

after the falling edge of CE# without impact on t

.

ELQV– GLQV

ELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 32.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

30

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Read Operations, continued

Density

Product

64 Mbit

90 ns

2.7 V–3.6 V

100 ns

#

Sym

Parameter

Unit

V

2.7 V–3.6 V

CC

Note

Min

Max

Min

Max

R1

R2

R3

R4

R5

R6

R7

R8

R9

t

Read Cycle Time

90

100

ns

AVAV

t

Address to Output Delay

CE# to Output Delay

OE# to Output Delay

RP# to Output Delay

CE# to Output in Low Z

OE# to Output in Low Z

CE# to Output in High Z

OE# to Output in High Z

90

100

20

AVQV

ELQV

GLQV

PHQV

1

t

20

t

150

t

2

0

ELQX

GLQX

EHQZ

GHQZ

t

20

t

Output Hold from Address, CE#, or OE#

Change, Whichever Occurs First

R10

t

2

0

ns

OH

NOTES:

1. OE# may be delayed up to t

t

after the falling edge of CE# without impact on t

.

ELQV– GLQV

ELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 32.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

3UHOLPLQDU\

31

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 8. AC Waveform: Read Operations

Device

Address Selection

Standby

Data Valid

V_IH

Address Stable

ADDRESSES (A)

CE# (E)

V_IL

V_IH

R1

V_IL

R8

R9

V_IH

V_IL

OE# (G)

V_IH

V_IL

WE# (W)

R4

R3

R7

R10

V_OH

V_OL

R6

High Z

DATA (D/Q)

Valid Output

R2

V_IH

V_IL

RP# (P)

R5

32

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.6

AC Characteristics—Write Operations

Density

Product

8 Mbit

90 ns

110 ns

100

#

Sym

Parameter

3.0 V – 3.6 V

2.7 V – 3.6 V

80

Unit

90

110

Min

Note

Min

t

/

PHWL

PHEL

W1

W2

W3

W4

W5

W6

W7

W8

W9

RP# High Recovery to WE# (CE#) Going Low

CE# (WE#) Setup to WE# (CE#) Going Low

WE# (CE#) Pulse Width

150

0

150

0

ns

t

/

ELWL

WLEL

0

50

0

70

60

70

0

t

/

WLWH

ELEH

1

2

60

50

60

0

70

60

70

0

t

/

DVWH

DVEH

Data Setup to WE# (CE#) Going High

Address Setup to WE# (CE#) Going High

CE# (WE#) Hold Time from WE# (CE#) High

Data Hold Time from WE# (CE#) High

Address Hold Time from WE# (CE#) High

WE# (CE#) Pulse Width High

t

/

AVWH

AVEH

t

/

WHEH

EHWH

t

WHDX

EHDX

2

1

0

t

WHAX

EHAX

0

t

WHWL /

EHEL

30

t

/

VPWH

VPEH

W10

W11

W12

V

Setup to WE# (CE#) Going High

Hold from Valid SRD

3

200

0

200

0

200

0

200

0

ns

PP

t

QVVL

t

/

BHWH

BHEH

WP# Setup to WE# (CE#) Going High

0

W13

W14

t

WP# Hold from Valid SRD

3

0

ns

QVBL

WE# High to OE# Going Low

30

WHGL

NOTES:

1. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WP

high (whichever goes high first). Hence, t

= t

. Similarly, write pulse width

WP

WLWH

ELEH

WLEH

ELWH

high (t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

(whichever goes low first). Hence, t

= t

.

WPH

WHWL

EHEL

WHEL

EHWL

2. Refer to Table 5, “Command Bus Operations” on page 13 for valid A or D

.

IN

3. Sampled, but not 100% tested.

Write timing characteristics during erase suspend are the same as during write-only operations.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

See Figure 8, “AC Waveform: Read Operations” on page 32.

4. V Max = 3.3 V for 32-Mbit and 64-Mbit densities.

CC

3UHOLPLQDU\

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28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Write Operations, continued

Density

Product

16 Mbit

90 ns

70 ns 80 ns

110 ns

100

#

Sym

Parameter

3.0 V – 3.6 V

2.7 V – 3.6 V

80

Unit

70

80

90

110

Min

Note

Min

t

/

RP# High Recovery to WE#

(CE#) Going Low

PHWL

PHEL

W1

W2

W3

W4

W5

W6

W7

W8

W9

150

0

150

0

150

0

150

0

ns

t

/

CE# (WE#) Setup to WE#

(CE#) Going Low

ELWL

WLEL

0

50

0

70

60

70

0

t

/

WLWH

ELEH

WE# (CE#) Pulse Width

1

2

45

40

50

0

50

40

50

0

60

50

60

0

70

60

70

0

t

/

Data Setup to WE# (CE#)

Going High

DVWH

DVEH

t

/

Address Setup to WE# (CE#)

Going High

AVWH

AVEH

t

/

CE# (WE#) Hold Time from

WE# (CE#) High

WHEH

EHWH

t

Data Hold Time from WE#

(CE#) High

WHDX

EHDX

2

1

0

t

Address Hold Time from WE#

(CE#) High

WHAX

EHAX

0

t

WHWL /

EHEL

WE# (CE#) Pulse Width High

25

30

t

/

V

Setup to WE# (CE#)

PP

VPWH

VPEH

W10

W11

W12

3

200

0

200

0

200

0

200

0

200

0

200

0

ns

Going High

t

V

PP

Hold from Valid SRD

QVVL

t

/

WP# Setup to WE# (CE#)

Going High

BHWH

BHEH

0

W13

W14

t

WP# Hold from Valid SRD

3

0

ns

QVBL

WE# High to OE# Going Low

30

WHGL

NOTES:

1. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going

WP

high (whichever goes high first). Hence, t

= t

. Similarly, write pulse width

WP

WLWH

ELEH

WLEH

ELWH

high (t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

(whichever goes low first). Hence, t

= t

.

WPH

WHWL

EHEL

WHEL

EHWL

2. Refer to Table 5, “Command Bus Operations” on page 13 for valid A or D

.

IN

3. Sampled, but not 100% tested.

Write timing characteristics during erase suspend are the same as during write-only operations.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

See Figure 8, “AC Waveform: Read Operations” on page 32.

4. V Max = 3.3 V for 32-Mbit and 64-Mbit densities.

CC

34

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Write Operations, continued

Density

Product

32 Mbit

100 ns

70 ns

90 ns

110 ns

100

#

Sym

Parameter

3.0 V – 3.6 V⁽⁴⁾

2.7 V – 3.6 V⁽⁴⁾

Note

90

Unit

70

90

100

Min

110

Min

t

/

RP# High Recovery to WE#

(CE#) Going Low

PHWL

PHEL

W1

W2

W3

W4

W5

W6

W7

W8

W9

150

0

150

0

150

0

150

0

ns

t

/

CE# (WE#) Setup to WE#

(CE#) Going Low

ELWL

WLEL

0

60

50

60

0

70

60

70

0

t

/

WLWH

ELEH

WE# (CE#) Pulse Width

1

2

45

40

50

0

60

40

60

0

70

60

70

0

70

60

70

0

t

/

Data Setup to WE# (CE#)

Going High

DVWH

DVEH

t

/

Address Setup to WE# (CE#)

Going High

AVWH

AVEH

t

/

CE# (WE#) Hold Time from

WE# (CE#) High

WHEH

EHWH

t

Data Hold Time from WE#

(CE#) High

WHDX

EHDX

2

1

0

t

Address Hold Time from WE#

(CE#) High

WHAX

EHAX

0

t

WHWL /

EHEL

WE# (CE#) Pulse Width High

25

30

t

/

V

Setup to WE# (CE#)

PP

VPWH

VPEH

W10

W11

W12

3

200

0

200

0

200

0

200

0

200

0

200

0

ns

Going High

t

V

PP

Hold from Valid SRD

QVVL

t

/

WP# Setup to WE# (CE#)

Going High

BHWH

BHEH

0

W13

W14

t

WP# Hold from Valid SRD

3

0

ns

QVBL

WE# High to OE# Going Low

30

WHGL

NOTES:

1. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WP

high (whichever goes high first). Hence, t

= t

. Similarly, write pulse width

WP

WLWH

ELEH

WLEH

ELWH

high (t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

(whichever goes low first). Hence, t

= t

.

WPH

WHWL

EHEL

WHEL

EHWL

2. Refer to Table 5, “Command Bus Operations” on page 13 for valid A or D

.

IN

3. Sampled, but not 100% tested.

Write timing characteristics during erase suspend are the same as during write-only operations.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

See Figure 8, “AC Waveform: Read Operations” on page 32.

4. V Max = 3.3 V for 0.25µm 32-Mbit devices.

CC

3UHOLPLQDU\

35

28F800C3, 28F160C3, 28F320C3, 28F640C3

AC Characteristics—Write Operations, continued

Density

Product

64 Mbit

90 ns

100 ns

100

#

Sym

Parameter

Unit

2.7 V – 3.6 V

90

Note

Min

t

/

PHWL

PHEL

W1

W2

W3

W4

W5

W6

W7

W8

W9

RP# High Recovery to WE# (CE#) Going Low

CE# (WE#) Setup to WE# (CE#) Going Low

WE# (CE#) Pulse Width

150

0

150

0

ns

t

/

ELWL

WLEL

t

/

WLWH

ELEH

1

2

60

40

60

0

70

40

60

0

t

/

DVWH

DVEH

Data Setup to WE# (CE#) Going High

Address Setup to WE# (CE#) Going High

CE# (WE#) Hold Time from WE# (CE#) High

Data Hold Time from WE# (CE#) High

Address Hold Time from WE# (CE#) High

WE# (CE#) Pulse Width High

t

/

AVWH

AVEH

t

/

WHEH

EHWH

t

WHDX

EHDX

2

1

0

t

WHAX

EHAX

0

t

WHWL /

EHEL

30

t

/

VPWH

VPEH

W10

W11

W12

V

Setup to WE# (CE#) Going High

Hold from Valid SRD

3

200

0

200

0

ns

PP

t

QVVL

PP

t

/

BHWH

BHEH

WP# Setup to WE# (CE#) Going High

0

W13

W14

t

WP# Hold from Valid SRD

3

0

ns

QVBL

WE# High to OE# Going Low

30

WHGL

NOTES:

1. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going

WP

high (whichever goes high first). Hence, t

= t

. Similarly, write pulse width

WP

WLWH

ELEH

WLEH

ELWH

high (t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

(whichever goes low first). Hence, t

= t

.

WPH

WHWL

EHEL

WHEL

EHWL

2. Refer to Table 5, “Command Bus Operations” on page 13 for valid A or D

.

IN

3. Sampled, but not 100% tested.

Write timing characteristics during erase suspend are the same as during write-only operations.

See Figure 6, “Input/Output Reference Waveform” on page 27 for timing measurements and maximum

allowable input slew rate.

See Figure 8, “AC Waveform: Read Operations” on page 32.

36

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.7

Erase and Program Timings

V

1.65 V–3.6 V

11.4 V–12.6 V

PP

Symbol

Parameter

Unit

Note

Typ⁽¹⁾

Max

Typ⁽¹⁾

Max

4-KW Parameter Block

Word Program Time

t

2, 3

0.10

0.8

12

0.30

0.03

0.12

s

BWPB

32-KW Main Block

Word Program Time

2, 3

2.4

200

4

0.24

8

1

185

4

BWMB

Word Program Time for 0.18

Micron Product

µs

s

t

/ t

WHQV1 EHQV1

Word Program Time for 0.25

Micron Product

22

8

4-KW Parameter Block

Erase Time

t

/ t

0.5

1

0.4

0.6

WHQV2 EHQV2

32-KW Main Block

Erase Time

/ t

5

s

WHQV3 EHQV3

t

/ t

Program Suspend Latency

Erase Suspend Latency

3

5

10

20

5

10

20

µs

WHRH1 EHRH1

/ t

WHRH2 EHRH2

NOTES:

1. Typical values measured at T = +25 °C and nominal voltages.

A

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

3UHOLPLQDU\

37

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 9. AC Waveform: Program and Erase Operations

A

B

C

D

E

F

V_IH

V_IL

ADDRESSES [A]

A_IN

W5

W8

(Note 1)

V_IH

CE# (WE#) [E(W)]

OE# [G]

V_IL

V_IH

W2

W6

V_IL

W14

W9

(Note 1)

V_IH

V_IL

WE# (CE) [W(E)]

W3

W4

W7

V_IH

V_IL

High Z

W1

Valid

SRD

DATA [D/Q]

D_IN

V_IH

V_IL

RP# [P]

WP#

W12

W13

W11

V_IH

V_IL

W10

V_PPH

2

1

V_PPH

V_PP[V]

V_PPLK

V_IL

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading

Status Register Data.

a. V Power-Up and Standby.

CC

b. Write Program or Erase Setup Command.

c. Write Valid Address and Data (for Program) or Erase Confirm Command.

d. Automated Program or Erase Delay.

e. Read Status Register Data (SRD): reflects completed program/erase operation.

f. Write Read Array Command.

38

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

4.8

Reset Operations

Figure 10. AC Waveform: Reset Operations

V

IH

RP# (P)

t_PHQV

t_PHWL

t_PHEL

V_IL

t_PLPH

(A) Reset during Read Mode

Abort

Complete

t_PHQV

t_PHWL

t_PHEL

t _PLRH

V_IH

V_IL

RP# (P)

t _PLPH

t_PLPH

t _PLRH

<

(B) Reset during Program or Block Erase,

Abort Deep

Complete Power-

t_PHQV

t_PHWL

t_PHEL

Down

t _PLRH

V_IH

V_IL

RP# (P)

t _PLPH

(C) Reset Program or Block Erase,

>

t_PLPHt _PLRH

Table 11. Reset Specifications

V

2.7 V – 3.6 V

Max

CC

Symbol

Parameter

Notes

Unit

Min

RP# Low to Reset during Read

t

(If RP# is tied to V , this specification is not

2,4

100

ns

PLPH

CC

applicable)

t

RP# Low to Reset during Block Erase

RP# Low to Reset during Program

3,4

22

µs

PLRH1

t

3,4

12

PLRH2

NOTES:

1. If t

is < 100 ns the device may still reset but this is not guaranteed.

PLPH

2. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete

within 100 ns.

3. Sampled, but not 100% tested.

See Section 3.1.4 for a full description of these conditions.

3UHOLPLQDU\

39

28F800C3, 28F160C3, 28F320C3, 28F640C3

5.0

Ordering Information

T E 2 8 F 3 2 0 C 3 T C 7 0

Access Speed (ns)

(70, 80, 90, 100, 110)

Package

TE = 48-Lead TSOP

GT = 48-Ball µBGA* CSP

GE = VF BGA CSP

RC = Easy BGA

Lithography

A = 0.25 µm

C = 0.18 µm

Product line designator

for all Intel^®Flash products

T = Top Blocking

B = Bottom Blocking

Device Density

640 = x16 (64 Mbit)

320 = x16 (32 Mbit)

160 = x16 (16 Mbit)

800 = x16 (8 Mbit)

Product Family

C3 = 3 Volt Advanced+ Boot Block

V_CC= 2.7 V–3.6 V

V_PP= 2.7 V–3.6 V or

11.4 V–12.6 V

VALID COMBINATIONS (All Extended Temperature)

48-Lead TSOP

48-Ball µBGA* CSP

48-Ball VF BGA

Easy BGA

TE28F640C3TC90

TE28F640C3BC90

GT28F640C3TC90

GT28F640C3BC90

RC28F640C3TC90

RC28F640C3BC90

Extended

64 Mbit

TE28F640C3TC100

TE28F640C3BC100

GT28F640C3TC100

GT28F640C3BC100

RC28F640C3TC100

RC28F640C3BC100

TE28F320C3TC70

TE28F320C3BC70

GE28F320C3TC70

GE28F320C3BC70

RC28F320C3TC70

RC28F320C3BC70

TE28F320C3TC90

TE28F320C3BC90

GE28F320C3TC90

GE28F320C3BC90

RC28F320C3TC90

RC28F320C3BC90

Extended

32 Mbit

TE28F320C3TA100

TE28F320C3BA100

GT28F320C3TA100

GT28F320C3BA100

RC28F320C3TA100

RC28F320C3BA100

TE28F320C3TA110

TE28F320C3BA110

GT28F320C3TA110

GT28F320C3BA110

RC28F320C3TA110

RC28F320C3BA110

TE28F160C3TC70

TE28F160C3BC70

GE28F160C3TC70

GE28F160C3BC70

RC28F160C3TC70

RC28F160C3BC70

TE28F160C3TC80

TE28F160C3BC80

GE28F160C3TC80

GE28F160C3BC80

RC28F160C3TC80

RC28F160C3BC80

Extended

16 Mbit

TE28F160C3TA90

TE28F160C3BA90

GT28F160C3TA90

GT28F160C3BA90

RC28F160C3TA90

RC28F160C3BA90

TE28F160C3TA110

TE28F160C3BA110

GT28F160C3TA110

GT28F160C3BA110

RC28F160C3TA110

RC28F160C3BA110

TE28F800C3TA90

TE28F800C3BA90

RC28F800C3TA90

RC28F800C3BA90

Extended

8 Mbit

TE28F800C3TA110

TE28F800C3BA110

RC28F800C3TA110

RC28F800C3BA110

NOTE:

1. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the

first character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other

assembly codes without an “E” or “S” as the first character are production units.

40

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

6.0

Additional Information

Order Number

Document/Tool

297938

292216

3 Volt Advanced+ Boot Block Flash Memory Specification Update

AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory

AP-657 Designing with the Advanced+ Boot Block Flash Memory

Architecture

292215

Contact your Intel

Representative

Intel^®Flash Data Integrator (IFDI) Software Developer’s Kit

297874

IFDI Interactive: Play with Intel^®Flash Data Integrator on Your PC

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical

documentation and tools.

3UHOLPLQDU\

41

28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix A WSM Current/Next States, Sheet 1 of 2

Command Input (and Next State)

Data

When

Read

Array

(FFH)

Program

Setup (10/

40H)

Erase

Setup

(20H)

Erase

Confirm

(D0H)

Prog/Ers

Suspend

(B0H)

Prog/Ers

Resume

(D0)

Read

Status

(70H)

Clear

Status

(50H)

SR.

7

Current State

Read Array

Read Status

Read Config.

Read Query

“1”

Array

Status

Config

CFI

Read Array

Prog. Setup

Ers. Setup

Read Array

Read Sts.

Read Array

Lock

(Done)

Lock

Cmd. Error

Lock

(Done)

Lock Setup

“1”

Status

Lock Command Error

Lock Cmd. Error

Lock Oper. (Done)

Prot. Prog. Setup

“1”

Status

Read Array

Prog. Setup

Ers. Setup

Read Array

Read Sts.

Read Array

Protection Register Program

Prot. Prog.

(Not Done)

“0”

Status

Protection Register Program (Not Done)

Prot. Prog. (Done)

Prog. Setup

“1”

Status

Read Array

Prog. Setup

Ers. Setup

Read Array

Program

Read Sts.

Read Array

Program (Not

Done)

Prog. Sus.

Status

“0”

“1”

Status

Array

Config

CFI

Program (Not Done)

Prog. Sus.

Read Array

Program Suspend

Read Array

Prog. (Not

Done)

Prog. Sus.

Rd. Array

Program

Prog.Sus.

Status

Prog. Sus.

Rd. Array

Prog. Susp. Status

(Not Done)

Prog. Susp. Read

Array

Prog. Sus.

Read Array

Program Suspend

Read Array

Prog. (Not

Done)

Prog. Sus.

Rd. Array

Program

(Not Done)

Prog.Sus.

Status

Prog. Sus.

Rd. Array

Prog. Susp. Read

Config

Prog. Sus.

Read Array

Program Suspend

Read Array

Prog. (Not

Done)

Prog. Sus.

Rd. Array

Program

(Not Done)

Prog.Sus.

Status

Prog. Sus.

Rd. Array

Prog. Susp. Read

Query

Prog. Sus.

Read Array

Program Suspend

Read Array

Prog. (Not

Done)

Prog. Sus.

Rd. Array

Program

(Not Done)

Prog.Sus.

Status

Prog. Sus.

Rd. Array

Read

Status

Program (Done)

Erase Setup

Status

Read Array

Prog. Setup

Ers. Setup

Read Array

Erase

(Not

Done)

Erase Cmd.

Error

Erase

(Not Done)

“1”

Status

Erase Command Error

Read

Erase Cmd. Error

Erase (Not Done)

Ers. Susp. Status

Erase Susp. Array

“1”

“0”

“1”

Status

Array

Read Array

Prog. Setup

Read Array

Status

Erase Sus.

Status

Erase (Not Done)

EraseSus.

Read Array

Ers. Sus.

Rd. Array

Ers. Sus.

Rd. Array

EraseSus.

Status

Ers. Sus.

Rd. Array

Prog. Setup

Erase

EraseSus.

Read Array

Ers. Sus.

Rd. Array

Ers. Sus.

Rd. Array

EraseSus.

Status

Ers. Sus.

Rd. Array

Ers. Susp. Read

Config

EraseSus.

Read Array

Ers. Sus.

Rd. Array

Ers. Sus.

Rd. Array

EraseSus.

Status

Ers. Sus.

Rd. Array

Config

Ers. Susp. Read

Query

EraseSus.

Read Array

Ers. Sus.

Rd. Array

Ers. Sus.

Rd. Array

EraseSus.

Status

Ers. Sus.

Rd. Array

“1”

CFI

Prog. Setup

Erase (Done)

Status

Read Array

Ers. Setup

Read Array

Read Sts.

Read Array

42

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix A: WSM Current/Next States, Sheet 2 of 2

Command Input (and Next State)

Lock Setup

(60H)

Lock Down

Confirm

(2FH)

Read Config

(90H)

Read Query

(98H)

Prot. Prog.

Setup (C0H)

Lock Confirm

(01H)

Unlock Confirm

(D0H)

Current State

Read Array

Read Status

Read Config.

Read Query

Lock Setup

Read Config.

Read Query

Lock Setup

Prot. Prog. Setup

Read Array

Locking Command Error

Lock Operation (Done)

Read Array

Lock Cmd. Error

Read Config.

Read Query

Lock Setup

Prot. Prog. Setup

Lock Oper.

(Done)

Read Array

Prot. Prog. Setup

Protection Register Program

Prot. Prog.

(Not Done)

Protection Register Program (Not Done)

Prot. Prog.

(Done)

Read Config.

Read Query

Lock Setup

Prot. Prog. Setup

Program

Read Array

Prog. Setup

Program

(Not Done)

Program (Not Done)

Prog. Susp.

Status

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Program Suspend Read Array

Prog. Susp.

Read Array

Prog. Susp.

Read Query

Program

Program Suspend Read Array

Read Config.

(Not Done)

Prog. Susp.

Read Config.

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Prog. Susp.

Read Query.

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Program

(Done)

Read Config.

Read Query

Lock Setup

Prot. Prog. Setup

Read Array

Erase

Setup

Erase

(Not Done)

Erase Command Error

Erase Cmd.

Error

Lock Setup

Prot. Prog. Setup

Erase (Not Done)

Erase

(Not Done)

Erase Susp.

Status

Ers. Susp. Read

Config.

Erase Suspend

Read Query

Erase

Lock Setup

Erase Suspend Read Array

(Not Done)

Erase Suspend

Array

Ers. Susp. Read

Config.

Erase Suspend

Read Query

Erase

(Not Done)

Erase Suspend Read Array

Eras Sus. Read

Config

Erase Suspend

Read Config.

Erase Suspend

Read Query

Erase

(Not Done)

Eras Sus. Read

Query

Erase Suspend

Read Config.

Erase Suspend

Read Query

Erase

(Not Done)

Lock Setup

Ers.(Done)

Read Config.

Read Query

Prot. Prog. Setup

Read Array

3UHOLPLQDU\

43

28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix B Program/Erase Flowcharts

Figure 11. Automated Word Programming Flowchart

Start

Bus Operation

Command

Program Setup

Program

Comments

Write

Data = 40H

Write 40H

Data = Data to Program

Addr = Location to Program

Write

Program Address/Data

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Repeat for subsequent programming operations.

No

SR.7 = 1?

Yes

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Standby

Command

Comments

Check SR.3

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4

1 = V_PPProgram Error

Standby

0

SR.4 =

0

Check SR.1

1

1 = Attempted Program to

Locked Block - Program

Aborted

Standby

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Block - Aborted

SR.1 =

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

44

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 12. Program Suspend/Resume Flowchart

Bus

Operation

Command

Comments

Data = B0H

Start

Program

Suspend

Write

Addr = X

Write B0H

Data=70H

Addr=X

Write

Read

Read Status

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write 70H

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Check SR.2

Standby

Write

1 = Program Suspended

0 = Program Completed

0

SR.7 =

Data = FFH

Addr = X

Read Array

1

0

Read array data from block

other than the one being

programmed.

SR.2 =

Program Completed

Read

1

Program

Resume

Data = D0H

Addr = X

Write

Write FFH

Read Array Data

No

Done

Reading

Yes

Write D0H

Write FFH

Program Resumed

Read Array Data

3UHOLPLQDU\

45

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 13. Automated Block Erase Flowchart

Start

Bus Operation

Command

Comments

Data = 20H

Write

Erase Setup

Addr = Within Block to Be

Erased

Write 20H

Data = D0H

Write

Read

Erase Confirm

Addr = Within Block to Be

Erased

Write D0H and

Block Address

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read Status Register

Suspend

Erase Loop

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

No

0

Yes

SR.7 =

Suspend Erase

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

1

Full Status

Check if Desired

Write FFH after the last write operation to reset device to read array mode.

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

Standby

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4,5

Standby

Both 1 = Command Sequence

Error

0

SR.4,5 =

0

1

Check SR.5

1 = Block Erase Error

Command Sequence

Error

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

SR.5 =

0

Block Erase Error

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

Attempted Erase of

Locked Block - Aborted

SR.1 =

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Block Erase

Successful

46

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 14. Erase Suspend/Resume Flowchart

Bus

Operation

Command

Erase Suspend

Read Status

Comments

Data = B0H

Start

Write

Addr = X

Write B0H

Data=70H

Addr=X

Write

Read

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write 70H

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

Write

1 = Erase Suspended

0 = Erase Completed

0

SR.7 =

Data = FFH

Addr = X

Read Array

1

0

Read array data from block

other than the one being

erased.

SR.6 =

Erase Completed

Read

1

Data = D0H

Addr = X

Write

Erase Resume

Write FFH

Read Array Data

No

Done

Reading

Yes

Write D0H

Write FFH

Erase Resumed

Read Array Data

3UHOLPLQDU\

47

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 15. Locking Operations Flowchart

Bus

Operation

Command

Comments

Data = 60H

Start

Write

Config. Setup

Addr = X

Write 60H

(Configuration Setup)

Data= 01H (Lock Block)

D0H (Unlock Block)

2FH (Lockdown Block)

Addr=Within block to lock

Lock, Unlock,

or Lockdown

Write

01H, D0H, or 2FH

Write

Read

Data = 90H

(Optional)

Configuration Addr = X

Read

(Optional)

Block Lock

Status

Block Lock Status Data

Addr = Second addr of block

Write 90H

(Read Configuration)

Confirm Locking Change on

DQ₁, DQ₀. (See Block Locking

State Table for valid

Standby

(Optional)

combinations.)

Read Block Lock Status

Locking

Change

Confirmed?

No

Write FFh

(Read Array)

Locking Change

Complete

48

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Figure 16. Protection Register Programming Flowchart

Start

Bus Operation

Write

Command

Comments

Protection Program

Setup

Data = C0H

Write C0H

(Protection Reg.

Program Setup)

Data = Data to Program

Addr = Location to Program

Write

Protection Program

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write Protect. Register

Address/Data

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Protection Program operations can only be addressed within the protection

register address space. Addresses outside the defined space will return an

error.

No

SR.7 = 1?

Yes

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Full Status

Check if Desired

Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Standby

Command

Comments

SR.1 SR.3 SR.4

Read Status Register

Data (See Above)

0

1

V_PPLow

1, 1

0

1

Prot. Reg.

Prog. Error

Standby

SR.3, SR.4 =

SR.1, SR.4 =

V_PPRange Error

1

0

1

Register

Locked:

Aborted

0,1

1,1

Standby

Protection Register

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Register -

Aborted

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

SR.1, SR.4 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

3UHOLPLQDU\

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix C Common Flash Interface Query Structure

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

C.1

Query Structure Output

The Query “database” allows system software to gain information for controlling the flash

component. This section describes the device’s CFI-compliant interface that allows the host system

to access Query data.

Query data are always presented on the lowest-order data outputs (DQ_0-7) only. The numerical

offset value is the address relative to the maximum bus width supported by the device. On this

family of devices, the Query table device starting address is a 10h, which is a word address for x16

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and ”R” in ASCII,

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H

data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ_0-7) and 00h in the

high byte (DQ_8-15).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table 12. Summary of Query Structure Output As a Function of Device and Mode

Hex

Offset

ASCII

Value

Device

Code

10:

11:

12:

51

52

59

“Q”

“R”

“Y”

Device Addresses

50

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Table 13. Example of Query Structure Output of x16 and x8 Devices

Word Addressing

Hex Code

Byte Addressing

Hex Code

Offset

–A

Value

Offset

Value

A

D

–D

A –A

D –D

7 0

15

0

15

0

7

0

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051

0052

0059

“Q”

“R”

10h

11h

12h

13h

14h

15h

16h

17h

18h

...

51

52

“Q”

“R”

“Y”

59

“Y”

P_ID

PrVendor

ID #

P_ID

PrVendor

ID #

LO

P_ID

HI

LO

P

PrVendor

TblAdr

AltVendor

ID #

P_ID

...

ID #

LO

HI

P

...

HI

A_ID

LO

A_ID

...

HI

...

C.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below.

Table 14. Query Structure⁽¹⁾

Offset

Sub-Section Name

Description

Manufacturer Code

00h

01h

Device Code

(BA+2)h⁽²⁾

04-0Fh

10h

Block Status Register

Reserved

Block-Specific Information

Reserved for Vendor-Specific Information

Command Set ID and Vendor Data Offset

Device Timing and Voltage Information

Flash Device Layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Vendor-Defined Additional Information

Specific to the Primary Vendor Algorithm

P⁽³⁾

Primary Intel-Specific Extended Query Table

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the

block size is 32 Kword).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

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28F800C3, 28F160C3, 28F320C3, 28F640C3

C.3

Block Lock Status Register

The Block Status Register indicates whether an erase operation completed successfully or whether

a given block is locked or can be accessed for flash program/erase operations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block erase

operation. BSR.1 can be used just after power-up to verify that the V_CCsupply was not

accidentally removed during an erase operation. This bit is only reset by issuing another erase

operation to the block. The Block Status Register is accessed from word address 02h within each

block.

Table 15. Block Status Register

Offset

(BA+2)h⁽¹⁾

Length

Description

Add.

Value

1

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

BA+2:

(bit 0): 0 or 1

1 = Locked

BSR.1 Block Lock-Down Status

0 = Not locked down

BA+2:

(bit 1): 0 or 1

1 = Locked down

BSR 2–7: Reserved for future use

BA+2:

(bit 2–7): 0

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word

mode.)

C.4

CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash

Interface specification. It also indicates the specification version and supported vendor-specified

command set(s).

Table 16. CFI Identification

Hex

Code

Offset

Length

Description

Add.

Value

10

11:

12:

--51

--52

--59

“Q”

“R”

“Y”

10h

3

Query-unique ASCII string “QRY“

Primary vendor command set and control interface ID code

16-bit ID code for vendor-specified algorithms

13:

14:

--03

--00

13h

15h

17h

19h

2

15:

16:

--35

--00

Extended Query Table primary algorithm address

Alternate vendor command set and control interface ID code

0000h means no second vendor-specified algorithm exists

17:

18:

--00

Secondary algorithm Extended Query Table address

0000h means none exists

19:

1A:

--00

52

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28F800C3, 28F160C3, 28F320C3, 28F640C3

C.5

System Interface Information

Table 17. System Interface Information

Hex

Code

Offset

Length

Description

Add.

Value

V

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1Bh

1Ch

1Dh

1Eh

1

1B:

--27

2.7 V

logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1

1C:

1D:

1E:

--36

--B4

--C6

3.6 V

11.4 V

12.6 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

[programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

1Fh

20h

21h

22h

23h

24h

25h

26h

1

“n” such that typical single word program time-out =2ⁿµs

“n” such that typical max. buffer write time-out = 2ⁿµs

“n” such that typical block erase time-out = 2ⁿms

1F:

20:

21:

22:

23:

24:

25:

26:

--05

--00

--0A

--00

--04

--00

--03

--00

32 µs

NA

1 s

“n” such that typical full chip erase time-out = 2ⁿms

NA

“n” such that maximum word program time-out = 2ⁿtimes typical

“n” such that maximum buffer write time-out = 2ⁿtimes typical

“n” such that maximum block erase time-out = 2ⁿtimes typical

“n” such that maximum chip erase time-out = 2ⁿtimes typical

512µs

NA

8s

NA

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28F800C3, 28F160C3, 28F320C3, 28F640C3

C.6

Device Geometry Definition

Table 18. Device Geometry Definition

Code

See table below

Offset

Length

Description

27h

1

“n” such that device size = 2ⁿin number of bytes

27:

28:

29:

Flash device interface:

x8 async x16 async x8/x16 async

--01

--00

x16

0

28h

2

28:00,29:00 28:01,29:00 28:02,29:00

2A:

2B:

--00

2Ah

2Ch

“n” such that maximum number of bytes in write buffer = 2ⁿ

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions

with one or more contiguous same-size erase blocks.

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

1

2C:

--02

2

2D:

2E:

2F:

30:

Erase Block Region 1 Information

2Dh

31h

4

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

31:

32:

33:

34:

Erase Block Region 2 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

Device Geometry Definition

8 Mbit

16 Mbit

32 Mbit

64 Mbit

Address

–B

–T

–B

–T

–B

–T

–B

–T

27:

28:

29:

2A:

2B:

2C:

2D:

2E:

2F:

30:

31:

32:

33:

34:

--14

--01

--00

--02

--07

--00

--20

--00

--0E

--00

--01

--14

--01

--00

--02

--0E

--00

--01

--07

--00

--20

--00

--15

--01

--00

--02

--07

--00

--20

--00

--1E

--00

--01

--15

--01

--00

--02

--1E

--00

--01

--07

--00

--20

--00

--16

--01

--00

--02

--07

--00

--20

--00

--3E

--00

--01

--16

--01

--00

--02

--3E

--00

--01

--07

--00

--20

--00

--17

--01

--00

--02

--07

--00

--20

--00

--7E

--00

--01

--17

--01

--00

--02

--7E

--00

--01

--07

--00

--20

--00

54

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

C.7

Intel-Specific Extended Query Table

Certain flash features and commands are optional. The Intel-Specific Extended Query table

specifies this and other similar types of information.

Table 19. Primary-Vendor Specific Extended Query

Offset(1)

P = 35h

Description

(Optional Flash Features and Commands)

Length

Address

Hex Code

Value

(P+0)h

(P+1)h

(P+2)h

35:

36:

37:

--50

--52

--49

“P”

“R”

“I”

Primary extended query table

Unique ASCII string “PRI”

3

(P+3)h

(P+4)h

1

Major version number, ASCII

Minor version number, ASCII

38:

39:

--31

--30

“1”

“0”

Optional feature and command support (1=yes,

0=no)

bits 9–31 are reserved; undefined bits are “0.” If

bit 31 is “1” then another 31 bit field of optional

features follows at the end of the bit-30 field.

3A:

3B:

3C:

3D:

--66

--00

(P+5)h

(P+6)h

(P+7)h

(P+8)h

bit 0 Chip erase supported

bit 0 = 0

No

Yes

No

bit 1 Suspend erase supported

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

bit 5 Instant individual block locking supported

bit 6 Protection bits supported

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 0

bit 8 = 0

4

No

Yes

No

bit 7 Page mode read supported

bit 8 Synchronous read supported

No

Supported functions after suspend: Read Array,

Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

3E:

--01

(P+9)h

1

bit 0 Program supported after erase suspend

bit 0 = 1

Yes

3F:

40:

--03

--00

Block status register mask

(P+A)h

(P+B)h

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status Register active

bit 1 Block Lock-Down Bit Status active

2

bit 0 = 1

bit 1 = 1

Yes

V

logic supply highest performance program/

CC

erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

(P+C)h

(P+D)h

1

41:

42:

--33

3.3 V

V

optimum program/erase supply voltage

PP

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

--C0

12.0 V

3UHOLPLQDU\

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Table 20. Protection Register Information

Offset(1)

P = 35h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Address

Value

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

(P+E)h

1

43:

--01

01

(P+F)h

(P+10)h

(P+11)h

44:

45:

46:

--80

--00

--03

80h

00h

8 byte

Protection Field 1: Protection Description

This field describes user-available One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device-

unique serial numbers. Others are user programmable. Bits 0–15

point to the Protection register Lock byte, the section’s first byte.

The following bytes are factory pre-programmed and user-

programmable.

4

(P+12)h

(P+13)h

47:

48:

--03

8 byte

bits 0–7 = Lock/bytes JEDEC-plane physical low address

bits 8–15 = Lock/bytes JEDEC -plane physical high address

bits 16–23 = “n” such that 2ⁿ= factory pre-programmed bytes

bits 24–31 = “n” such that 2ⁿ= user programmable bytes

Reserved for future use

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

56

3UHOLPLQDU\

28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix D Architecture Block Diagram

DQ₀-DQ₁₅

V_CCQ

Output Buffer

Input Buffer

Identifier

Register

Status

Register

I/O Logic

CE#

WE#

OE#

RP#

Command

User

Interface

Power

Reduction

Control

Data

Comparator

WP#

A₀-A₁₉

Y-Decoder

Y-Gating/Sensing

Write State

Machine

Program/Erase

Voltage Switch

Input Buffer

V_PP

Address

Latch

X-Decoder

V_CC

GND

Address

Counter

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix E Word-Wide Memory Map Diagrams

8-Mbit Word-Wide Memory Addressing

Top Boot

Bottom Boot

Size

(KW)

Size

(KW)

8 Mbit

4

7F000-7FFFF

7E000-7EFFF

7D000-7DFFF

7C000-7CFFF

7B000-7BFFF

7A000-7AFFF

79000-79FFF

78000-78FFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

32

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

4

32

58

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28F800C3, 28F160C3, 28F320C3, 28F640C3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

Size

(KW)

16 Mbit

32 Mbit

64 Mbit

16 Mbit

32 Mbit

64 Mbit

4

FF000-FFFFF

FE000-FEFFF

FD000-FDFFF

FC000-FCFFF

FB000-FBFFF

FA000-FAFFF

F9000-F9FFF

F8000-F8FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

1FF000-1FFFFF

1FE000-1FEFFF

1FD000-1FDFFF

1FC000-1FCFFF

1FB000-1FBFFF

1FA000-1FAFFF

1F9000-1F9FFF

1F8000-1F8FFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

3FF000-3FFFFF

3FE000-3FEFFF

3FD000-3FDFFF

3FC000-3FCFFF

3FB000-3FBFFF

3FA000-3FAFFF

3F9000-3F9FFF

3F8000-3F8FFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

32

3F8000-3FFFFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

4

32

This column continues on next page

3UHOLPLQDU\

59

28F800C3, 28F160C3, 28F320C3, 28F640C3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

Size

(KW)

16 Mbit

32 Mbit

64 Mbit

16 Mbit

32 Mbit

64 Mbit

32

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-21FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

32

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

F8000-FFFFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

C8000-CFFFF

C0000-C7FFF

This column continues on next page

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28F800C3, 28F160C3, 28F320C3, 28F640C3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

Size

(KW)

16 Mbit

32 Mbit

64 Mbit

16 Mbit

32 Mbit

64 Mbit

32

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

32

4

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

4

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix F Device ID Table

Read Configuration Addresses and Data

Item

Address

Data

Manufacturer Code

Device Code

x16

00000

0089

8-Mbit x 16-T

x16

00001

88C0

88C1

88C2

88C3

88C4

88C5

88CC

88CD

8-Mbit x 16-B

16-Mbit x 16-T

16-Mbit x 16-B

32-Mbit x 16-T

32-Mbit x 16-B

64-Mbit x 16-T

64-Mbit x 16-B

NOTE: Other locations within the configuration address space are reserved by Intel for future use.

62

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28F800C3, 28F160C3, 28F320C3, 28F640C3

Appendix G Protection Register Addressing

Word-Wide Protection Register Addressing

Word

Use

A7

A6

A5

A4

A3

A2

A1

A0

LOCK

Both

Factory

User

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

User

NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,

i.e., A A = 0.

21–

8

3UHOLPLQDU\

63

型号：	GT28F640C3TC100
PDF下载：	下载PDF文件查看货源
内容描述：	[Flash, 4MX16, 100ns, PBGA48, CSP, MICRO, BGA-48]
分类和应用：	内存集成电路
文件页数/大小：	70 页 / 945 K
品牌：	NUMONYX [ NUMONYX B.V ]

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