1.8 Volt Intel StrataFlash
®
Wireless
Memory (L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
s
High performance Read-While-Write/Erase
— 85 ns initial access
— 54MHz with zero wait state, 14 ns clock-to-data
output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 10 µs/byte (Typ)
s
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions
— Four 16-KWord parameter blocks: top or
bottom configurations
— 64-KWord main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
s
Power
— 1.7 V - 2.0 V V
CC
operation
— I/O voltage: 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 25 µA (Typ)
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— Automatic Power Savings (APS) mode
s
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
s
Security
•
OTP space:
— 64 unique device identifier bits
— 64 user-programmable OTP bits
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: V
PP
= GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
s
Quality and Reliability
— Expanded temperature: –25° C – +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
s
Density and Packaging
— 64-, 128- and 256-Mbit density in VF BGA
packages
— 16-bit wide data bus
The 1.8 Volt Intel StrataFlash
®
wireless memory
product is the latest generation of Intel StrataFlash
®
memory devices featuring flexible, multiple-partition, dual operation. It provides high performance
asynchronous read mode and synchronous-burst read mode using 1.8 volt low-voltage, multi-level cell
(MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background. The 8-Mbit partitions allow system designers to choose the size of the code and data segments.
The 1
.8 Volt Intel StrataFlash
®
wireless memory
device is manufactured using Intel 0.13 µm ETOX™
VIII process technology. It is available in industry-standard chip scale packaging.
Notice:
This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251902
October 2002
NUMONYX [ NUMONYX B.V ]
