28F640L18, 28F128L18, 28F256L18
2.3
Signal Descriptions
Table 1 describes the active signals used on the L18 flash memory device.
Table 1. Signal Descriptions
Symbol
Type
In
Name and Function
A[MAX:0]
ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory,
Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are de-asserted. Data is internally latched during writes.
D[15:0]
In/Out
ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
CE#
In
In
CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it
in standby, with D[15:0] and WAIT in High-Z.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and
increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
CLK
In
OUTPUT ENABLE: Active-low input. OE#-low enables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z.
OE#
In
In
RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read array mode.
RST#
WAIT: Wait is driven when CE# is asserted. RCR[10] [WP] determines the WAIT -asserted logic level.
•
In synchronous array read modes, WAIT indicates invalid data when asserted and valid data when
de-asserted.
WAIT
Out
•
In synchronous non-array read modes, asynchronous page mode, and all write modes, WAIT is
asserted.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of WE#.
WE#
WP#
In
In
WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
ERASE/ PROGRAM POWER: Valid V voltages on this ball allow block erase and program functions.
PP
VPP
Pwr
Flash memory array contents cannot be altered when V ≤ V
. Block erase and program at invalid
PP
PPLK
V
voltages should not be attempted.
PP
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when V ≤ V . Operations at invalid V voltages should not be attempted.
VCC
Pwr
Pwr
CC
LKO
CC
OUTPUT POWER SUPPLY: Output-driver source voltage. This ball can be tied directly to V if
CC
VCCQ
operating within V range.
CC
VSS
Pwr
Pwr
GROUND: Ground reference for device logic voltages. Connect to system ground.
GROUND: Ground reference for device output voltages. Connect to system ground.
VSSQ
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
D
U
-
RFU
-
RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement.
Datasheet
11
NUMONYX [ NUMONYX B.V ]
