28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.2
Conventions
Table 2.
Conventions
Convention
Description
Used interchangeably to refer to the external signal connections on the
package.
Pin or signal
Note: For a chip scale package (CSP), the term ball is used in place of pin.
Square brackets designate group membership or define a group of signals
with similar function (for example, A[21:1], SR[4:1])
Group Membership Brackets
Set
When referring to registers, the term set means the bit is a logical 1.
When referring to registers, the term clear means the bit is a logical 0.
Clear:
A group of bits (or words) that erase simultaneously using one block erase
instruction.
Block
Main Block
A block that contains 32 Kwords.
A block that contains 4 Kwords.
Parameter Block
2.0
Functional Overview
The B3 flash memory device features the following:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility.
• Program Suspend to Read command.
• V
input of 1.65 V to 2.5 V or 2.7 V to 3.6 V on all I/Os. See Figure 1 through Figure 4 for
CCQ
pinout diagrams and V
location.
CCQ
• Maximum program and erase time specification for improved data storage.
Table 3.
B3 Device Feature Summary (Sheet 1 of 2)
28F800B3, 28F160B3,
Feature
28F008B3, 28F016B3
Reference
28F320B3(3), 28F640B3
Section 6.2, Section
7.2
VCC Read Voltage
2.7 V– 3.6 V
V
CCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
Section 4.2, 4.4
Table 27
VPP Program/Erase Voltage
Bus Width
8 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
512 Kbit x 16 (8 Mbit),
16 bit
Speed
Section 8.1
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
Section 3.2
18 Aug 2005
8
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
NUMONYX [ NUMONYX B.V ]
