28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 3.
B3 Device Feature Summary (Sheet 2 of 2)
28F800B3, 28F160B3,
28F320B3(3), 28F640B3
Feature
28F008B3, 28F016B3
Reference
Eight 8-Kbyte parameter blocks and
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Section 3.2, “Memory
Maps and Block
Organization” on
page 11
Blocking (top or bottom)
Sixty-three 64-Kbyte main blocks (32 Mbit)
One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 12.0
Table 32
Locking
Section 6.2, Section
7.2
Operating Temperature
Program/Erase Cycling
Extended: –40 °C to +85 °C
Section 6.2, Section
7.2
100,000 cycles
48-Lead TSOP,
40-lead TSOP(1)
48-Ball µBGA* CSP(2)
,
Packages
48-Ball µBGA CSP(2)
,
Figure 8, Figure 9
48-Ball VF BGA
Notes:
1.
2.
3.
32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
8-Mbit densities not available in µBGA* CSP.
VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
3.0
Functional Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins:
• V for Read operation
CC
• V
for output swing
CCQ
• V for Program and Erase operation.
PP
All B3 flash memory devices provide program/erase capability at 2.7 V or 12 V (for fast
production programming), and read with V at 2.7 V. Because many designs read from the flash
CC
memory a large percentage of the time, 2.7 V V operation can provide substantial power
CC
savings.
The B3 flash memory device family is available in either x8 or x16 packages in the following
densities (see Appendix C, “Ordering Information,” for availability):
• 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024
Kbytes of 8-bits each.
• 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each.
• 32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each.
• 64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each.
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map, to accommodate different microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can be locked to provide complete code security
for system initialization code. Locking and unlocking is controlled by Write Protect WP# (see
Section 12.0, “Block Locking” on page 62 for details).
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
9
NUMONYX [ NUMONYX B.V ]
