E
28F004S5, 28F008S5, 28F016S5
2.0 PRINCIPLES OF OPERATION
1FFFFF
31
64-Kbyte Block
The 5 Volt FlashFile memories include an on-chip
WSM to manage block erase, program, and lock-bit
configuration functions. It allows for: 100% TTL-
level control inputs, fixed power supplies during
block erasure, program, and lock-bit configuration,
and minimal processor overhead with RAM-like
interface timings.
1F0000
1EFFFF
30
64-Kbyte Block
1E0000
1DFFFF
29
64-Kbyte Block
1D0000
1CFFFF
28
64-Kbyte Block
1C0000
1BFFFF
27
64-Kbyte Block
1B0000
1AFFFF
26
64-Kbyte Block
1A0000
19FFFF
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
standby, and output disable operations.
25
64-Kbyte Block
190000
18FFFF
24
64-Kbyte Block
180000
17FFFF
23
64-Kbyte Block
170000
16FFFF
22
64-Kbyte Block
160000
15FFFF
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure, program, and lock-bit configuration.
All functions associated with altering memory
21
64-Kbyte Block
150000
14FFFF
20
19
18
17
16
15
14
13
12
11
10
9
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
140000
13FFFF
130000
12FFFF
contents—block
erase,
program,
lock-bit
120000
11FFFF
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
110000
10FFFF
100000
0FFFFF
16-Mbit
0F0000
0EFFFF
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
8-Mbit
8
080000
07FFFF
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read data
from or program data to any other block. Program
suspend allows system software to suspend a
program to read data from any other flash memory
array location.
7
070000
06FFFF
6
060000
05FFFF
5
050000
04FFFF
4
040000
03FFFF
4-Mbit
3
030000
02FFFF
2
020000
01FFFF
1
010000
00FFFF
0
000000
Figure 4. Memory Map
9
PRELIMINARY
NUMONYX [ NUMONYX B.V ]
