Numonyx™ StrataFlash
®
Wireless Memory (L18 AD-Mux)
1.0
Introduction
This document provides information about the Numonyx™ StrataFlash
®
Wireless
Memory (L18) with AD-Multiplexed I/O device. This document describes device
features, operation, and specifications.
The Numonyx™ StrataFlash
®
Wireless Memory (L18) with AD-Multiplexed I/O product
is the latest generation of Intel StrataFlash
®
memory featuring flexible, multiple-
partition, dual operation. It provides high performance asynchronous read mode and
synchronous-burst read mode using 1.8 V low-voltage, multi-level cell (MLC)
technology.
The multiple-partition architecture enables background programming or erasing to
occur in one partition while code execution or data reads take place in another
partition. This dual-operation architecture also allows two processors to interleave code
operations while program and erase operations take place in the background. 8-Mbit
partitions allow system designers to choose the size of the code and data segments.
The Numonyx™ StrataFlash
®
Wireless Memory (L18) with AD-Multiplexed I/O device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology, available in
industry-standard chip scale packaging.
1.1
1.8 V
Nomenclature
Vcc voltage range of 1.7 V – 2.0 V (except where noted)
Vccq voltage range of 1.35 V – 2.0 V
VPP voltage range of 8.5 V – 9.5 V
1.8 V Extended Range
VPP = 9.0 V
Block
Main block
Parameter block
A group of bits, bytes or words within the flash memory array that erase simultaneously when the
Erase command is issued to the device. The device has two block sizes: 16K-Word and 64K-Word.
An array block that is usually used to store code and/or data. Main blocks are larger than parameter
blocks.
An array block that is usually used to store frequently changing data or small system parameters
that traditionally would be stored in EEPROM.
Previously referred to as a top-boot device, a device with its parameter partition located at the
highest physical address of its memory map. Parameter blocks within a parameter partition are
located at the highest physical address of the parameter partition.
A group of blocks that share common program/erase circuitry. Blocks within a partition also share a
common status register. If any block within a partition is being programmed or erased, only status
register data (rather than array data) is available when any address within that partition is read.
A partition containing only main blocks.
A partition containing parameter blocks and main blocks.
Top parameter device
Partition
Main partition
Parameter partition
1.2
CUI
MLC
OTP
PLR
PR
Acronyms
Command User Interface
Multi-Level Cell
One-Time Programmable
Protection Lock Register
Protection Register
November 2007
Order Number: 313295-04
Datasheet
7
NUMONYX [ NUMONYX B.V ]
