M29FxxxFT, M29FxxxFB
Figure 1.
Description
Logic Diagram
V
CC
20
15
DQ0-DQ07
DQ8-DQ15
A0-A19
W
E
DQ15A–1
G
RB
RP
BYTE
V
SS
AI06849B
Table 1.
Signal Names
Address Inputs
A0-A19
DQ0-DQ7
Data Inputs/Outputs
Data Inputs/Outputs
DQ8-DQ14
DQ15A–1
E
Data Input/Output or Address Input
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
RB
BYTE
VCC
VSS
NC
Ground
Not Connected Internally
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