Electrical Characteristics: (V+ = 5V, –55°C ≤ TA ≤ +125°C, unless otherwise specified)
Parameter
Input Offset Voltage
Input Bias Current
Test Conditions
TA = +25°C, Note 6
Min Typ
Max
±5.0
250
Unit
mV
nA
–
–
±2.0
IIN(+) or IIN(–) with Output in Linear Range,
TA = +25°C, Note 4
25
Input Offset Current
IIN(+) – IIN(–), TA = +25°C
–
±5.0
±50
V+ –1.5
nA
V
Input Common–Mode Voltage TA = +25°C, Note 5
0
–
Range
Supply Current
Voltage Gain
RL = ∞ on all Comparators, TA = +25°C
RL ≥ 15kΩ, V+ = 15V (To Support Large
VO Swing), TA = +25°C
–
–
0.8
2.0
mA
200
–
V/mV
Large Signal Response Time VIN = TTL Logic Swing, VREF = 1.4V,
RL = 5V, RL = 5.1kΩ, TA = +25°C
VRL = 5V, RL = 5.1kΩ, TA = +25°C
–
300
–
ns
V
Response Time
–
1.3
16
–
–
µs
Output Sink Current
V
IN(–) ≥ 1V, VIN(+) = 0, VO ≤ 1.5V,
TA = +25°C
IN(–) ≥ 1V, VIN(+) = 0, ISINK ≤ 4mA,
TA = +25°C
IN(+) ≥ 1V, VIN(–) = 0, VO = 5V,
6.0
mA
Saturation Voltage
V
–
–
250
0.1
400
mV
nA
Output Leakage Current
V
–
TA = +25°C
Input Offset Voltage
Input Offset Current
Input Bias Current
Note 6
–
–
–
0
–
–
–
–
9.0
±150
400
mVDC
nA
IIN(+) – IIN(–)
IIN(+) or IIN(–) with Output in Linear Range
nA
Input Common Mode Voltage
Range
V+ –2.0
V
Saturation Voltage
V
IN(–) ≥ 1V, VIN(+) = 0, ISINK ≤ 4mA
IN(+) ≥ 1V, VIN(–) = 0, VO = 30V
–
–
–
–
–
–
700
1.0
36
mV
µA
V
Output Leakage Current
Differential Input Voltage
V
All VIN’s ≥ 0V (or V–, if used)
Note 1 For operating at high temperatures, these devices must be derated based on a +125°C maxi-
mum junction temperature and a thermal resistance of +175°C/W which applies for the device
soldered to a printed circuit board, operating in ambient still air. The low bias dissipation and
the “ON–OFF” characteristic of the outputs keeps the chip dissipation very low (PD ≤ 100mW),
provided the output transistors are allowed to saturate.
Note 2 Short circuits from the output to V+ can cause excessive heating and eventual destruction.
The maximum output current is approximately 20mA independent of the magnitude of V+.
Note 3 This input current will only exist when the voltage at any of the input leads is driven negative.
It is due to the collector–base junction of the input PNP transistors becoming forward biased
and thereby acting as input diode clamps.
Note 4 The direction of the input current is out of the IC due to the PNP input stage. This current
is essentially constant, independent of the state of the output so no loading change exists
on the reference to input lines.
Note 5 The input common–mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common–mode voltage range is V+ –1.5V,
but either or both inputs can go to +30V without damage.
Note 6. At output switch point, VO 1.4V, RS = 0Ω with V+ from 5V; and over the full input common–
mode range (0V to V+ – 1.5V).
NTE [ NTE ELECTRONICS ]
