8.0 Registers
The system programmer may access any of the UART reg-
isters summarized in Table II via the CPU. These registers
control UART operations including transmission and recep-
tion of data. Each register bit in Table II has its name and
reset state shown.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1,
a Parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and Stop bit of the
serial data. (The Parity bit is used to produce an even or odd
number of 1s when the data word bits and the Parity bit are
summed.)
8.1 LINE CONTROL REGISTER
Bit 4: This bit is the Even Parity Select bit. When bit 3 is a
logic 1 and bit 4 is a logic 0, an odd number of logic 1s is
transmitted or checked in the data word bits and Parity bit.
When bit 3 is a logic 1 and bit 4 is a logic 1, an even number
of logic 1s is transmitted or checked.
The system programmer specifies the format of the asyn-
chronous data communications exchange and set the Divi-
sor Latch Access bit via the Line Control Register (LCR).
The programmer can also read the contents of the Line
Control Register. The read capability simplifies system pro-
gramming and eliminates the need for separate storage in
system memory of the line characteristics. Table II shows
the contents of the LCR. Details on each bit follow:
Bit 5: This bit is the Stick Parity bit. When bits 3, 4 and 5 are
logic 1 the Parity bit is transmitted and checked as a logic 0.
If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is
transmitted and checked as a logic 1. If bit 5 is a logic 0
Stick Parity is disabled.
Bits 0 and 1: These two bits specify the number of bits in
each transmitted or received serial character. The encoding
of bits 0 and 1 is as follows:
Bit 6: This bit is the Break Control bit. It causes a break
condition to be transmitted to the receiving UART. When it
is set to a logic 1, the serial output (SOUT) is forced to the
Spacing (logic 0) state. The break is disabled by setting bit 6
to a logic 0. The Break Control bit acts only on SOUT and
has no effect on the transmitter logic.
Bit 1
Bit 0
Character Length
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
Note: This feature enables the CPU to alert a terminal in a computer com-
munications system. If the following sequence is followed, no errone-
ous or extraneous characters will be transmitted because of the
break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
Bit 2: This bit specifies the number of Stop bits transmitted
and received in each serial character. If bit 2 is a logic 0,
one Stop bit is generated in the transmitted data. If bit 2 is a
logic 1 when a 5-bit word length is selected via bits 0 and 1,
one and a half Stop bits are generated. If bit 2 is a logic 1
when either a 6-, 7-, or 8-bit word length is selected, two
Stop bits are generated. The Receiver checks the first Stop-
bit only, regardless of the number of Stop bits selected.
e
3. Wait for the transmitter to be idle, (TEMT 1), and clear break when
normal transmission has to be restored.
During the break, the Transmitter can be used as a character timer to accu-
rately establish the break duration.
TABLE III. Baud Rates, Divisors and Crystals
1.8432 MHz Cystal 3.072 MHz Crystal
18.432 MHz Crystal
Decimal Divisor
c
for 16 Clock
Decimal Divisor
c
for 16 Clock
Decimal Divisor
c
for 16 Clock
Baud Rate
Percent Error
Percent Error
Percent Error
50
75
2304
1536
1047
857
768
384
192
96
Ð
Ð
3840
2560
1745
1428
1280
640
320
160
107
96
Ð
Ð
23040
15360
10473
8565
7680
3840
1920
920
640
576
480
320
240
160
120
60
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2.04
Ð
110
0.026
0.058
Ð
0.026
0.034
Ð
134.5
150
300
Ð
Ð
600
Ð
Ð
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
Ð
Ð
64
Ð
0.312
Ð
58
0.69
Ð
48
80
Ð
32
Ð
53
0.628
Ð
24
Ð
40
16
Ð
27
1.23
Ð
12
Ð
20
6
Ð
10
Ð
3
Ð
5
Ð
30
2
2.86
Ð
Ð
Ð
21
Ð
Ð
Ð
9
Note: For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a 24 MHz crystal causes minimal error.
15
NSC [ National Semiconductor ]
