LP3971
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
PWR_ON
nTEST_JIG
SPARE
EXT_WAKEUP
FB1
V
IN
V
OUT
LDO1
V
OUT
LDO2
nRSTI
GND1
V
REF
V
OUT
LDO3
V
OUT
LDO4
V
IN
LDO4
V
IN
BUBATT
V
OUT
LDO_RTC
nBATT_FLT
PGND2
SW2
V
IN
Buck2
SDA
SCL
FB2
nRSTO
V
OUT
LDO5
V
IN
LDO5
VDDA
FB3
GPIO1/nCHG_EN
GPIO2
V
IN
Buck3
SW3
PGND3
BGND1,2,3
SYNC
SYS_EN
PWR_EN
PGND1
SW1
V
IN
Buck1
I/O
I
I
I
O
I
I
O
O
I
G
O
O
O
I
I
O
O
G
O
I
I/O
I
I
O
O
I
I
I
I/O
I/O
I
O
G
G
I
I
I
G
O
I
Type
D
D
D
D
A
P
P
P
D
G
A
P
P
P
P
P
D
G
P
P
D
D
A
D
P
P
P
A
D
D
P
P
G
G
D
D
D
G
P
P
CPU Wakeup input
CPU Wakeup input
CPU Wakeup input
CPU Wakeup output
Buck1 Feedback
Battery Input (Internal circuitry and LDO1–3 power input)
LDO1 output
LDO2 output
Reset Input
Ground
Bypass Cap. for reference
LDO3 output
LDO4 output
Input power for LDO4
Back Up Battery input
LDO_RTC output
Main Battery fault output
Buck2 NMOS Power Ground
Buck2 Output
Buck2 battery input
I
2
C Data
I
2
C Clock
Buck2 Feedback
Reset output
LDO5 output
Input power for LDO5
Analog Power
Buck3 Feedback
General Purpose I/O/Ext. backup battery charger enable
General Purpose I/O
Buck3 battery input
Buck3 Output
Buck3 NMOS Power Ground
Bucks 1, 2 and 3 analog Ground
Bucks external clock input
High voltage domain enable
Low Voltage domain enable
Buck1 NMOS Power Ground
Buck1 Output
Buck1 battery input
Description
A: Analog Pin
D: Digital Pin
G: Ground Pin
P: Power Pin
I: Input Pin
I/O: Input/Output Pin
O: Output Pin
Note:
In this document active low logic items are prefixed with a lowercase “n”
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