Pin Descriptions
Pin
Name(s)
FAN1-FAN2
BTI
Pin
Number
4-5
6
(Continued)
Number
of Pins
2
1
Type
Digital Inputs
Digital Input
Description
0 to V
+
fan tachometer inputs.
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of
10 kΩ.
An active high input from an external circuit which latches a Chassis
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM80. The LM80 provides an
internal open drain on this line, controlled by Bit 5 of the
Configuration Register, to provide a minimum 10 ms reset of this
line.
Internally connected to all of the digital circuitry.
+3.3V or +5V V
+
power. Bypass with the parallel combination of
10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass
capacitors.
Non-Maskable Interrupt (open source)/Interrupt Request (open
drain). The mode is selected with Bit 5 of the Configuration Register
and the output is enabled when Bit 1 of the Configuration Register
is set to 1. The default state is disabled.
An active low open drain output intended to drive an external
P-channel power MOSFET for software power control.
An active-low input that enables NAND Tree board-level connectivity
testing. Refer to Section 10.0 on NAND Tree testing. Whenever
NAND Tree connectivity is enabled the LM80 is also reset to its
power on state.
Master Reset, 5 mA driver (open drain), active low output with a
10 ms minimum pulse width. Available when enabled via Bit 4 in
Configuration Register and Bit 7 of the Fan Divisor/RST_OUT/OS
Register. Bit 6 of the Fan Divisor/RST_OUT/OS Register enables
this output as an active low Overtemperature Shutdown (OS).
Internally connected to all analog circuitry. The ground reference for
all analog inputs. This pin needs to be taken to a low noise analog
ground plane for optimum performance.
0V to 2.56V full scale range Analog Inputs.
The lowest order bit of the Serial Bus Address. This pin functions as
an output when doing a NAND Tree test.
The two highest order bits of the Serial Bus Address.
CI (Chassis
Intrusion)
7
1
Digital I/O
GND
V
+
(+2.8V to
+5.75V)
INT
8
9
1
1
GROUND
POWER
10
1
Digital Output
GPO (Power
Switch Bypass)
NTEST_IN/
RESET_IN
11
12
1
1
Digital Output
Digital Input
RST_OUT/OS
13
1
Digital Output
GNDA
14
1
GROUND
IN6-IN0
A0/NTEST_OUT
A1-A2
TOTAL PINS
15-21
22
23-24
7
1
2
24
Analog Inputs
Digital I/O
Digital Inputs
3
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