Applications Information (Continued)
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors RA and RB may be con-
nected as in Figure 14. The time period for the output high is
the same as previous, t1 = 0.693 RA C. For the output low it
is t2
=
Thus the frequency of oscillation is
DS007851-18
FIGURE 14. 50% Duty Cycle Oscillator
Note that this circuit will not oscillate if RB is greater than 1/2
RA because the junction of RA and RB cannot bring pin 2
down to 1/3 VCC and trigger the lower comparator.
ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1µF in par-
allel with 1µF electrolytic.
Lower comparator storage time can be as long as 10µs
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10µs minimum.
Delay time reset to output is 0.47µs typical. Minimum reset
pulse width must be 0.3µs, typical.
Pin 7 current switches within 30ns of the output (pin 3) volt-
age.
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