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LM3940IMPX-3.3 参数 Datasheet PDF下载

LM3940IMPX-3.3图片预览
型号: LM3940IMPX-3.3
PDF下载: 下载PDF文件 查看货源
内容描述: [IC VREG 3.3 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, PDSO4, SOT-223, 3 PIN, Fixed Positive Single Output LDO Regulator]
分类和应用: 光电二极管输出元件调节器
文件页数/大小: 12 页 / 307 K
品牌: NSC [ National Semiconductor ]
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HEATSINKING  
Application Hints  
A heatsink may be required depending on the maximum pow-  
er dissipation and maximum ambient temperature of the ap-  
plication. Under all possible operating conditions, the junction  
temperature must be within the range specified under Abso-  
lute Maximum Ratings.  
EXTERNAL CAPACITORS  
The output capacitor is critical to maintaining regulator stabil-  
ity, and must meet the required conditions for both ESR  
(Equivalent Series Resistance) and minimum amount of ca-  
pacitance.  
To determine if a heatsink is required, the power dissipated  
by the regulator, PD, must be calculated.  
MINIMUM CAPACITANCE:  
The figure below shows the voltages and currents which are  
present in the circuit, as well as the formula for calculating the  
power dissipated in the regulator:  
The minimum output capacitance required to maintain stabil-  
ity is 33 μF (this value may be increased without limit). Larger  
values of output capacitance will give improved transient re-  
sponse.  
ESR LIMITS:  
The ESR of the output capacitor will cause loop instability if it  
is too high or too low. The acceptable range of ESR plotted  
versus load current is shown in the graph below. It is essen-  
tial that the output capacitor meet these requirements, or  
oscillations can result.  
1208006  
IIN = IL + IG  
PD = (VIN − VOUT) IL + (VIN) IG  
FIGURE 2. Power Dissipation Diagram  
The next parameter which must be calculated is the maximum  
allowable temperature rise, TR (max). This is calculated by  
using the formula:  
TR (max) = TJ (max) − TA (max)  
Where: TJ (max)  
is the maximum allowable junction tem-  
perature, which is 125°C for commercial  
grade parts.  
1208005  
TA (max)  
is the maximum ambient temperature  
which will be encountered in the applica-  
tion.  
FIGURE 1. ESR Limits  
It is important to note that for most capacitors, ESR is speci-  
fied only at room temperature. However, the designer must  
ensure that the ESR will stay inside the limits shown over the  
entire operating temperature range for the design.  
Using the calculated values for TR(max) and PD, the maxi-  
mum allowable value for the junction-to-ambient thermal re-  
sistance, θ(JA), can now be found:  
θ(JA) = TR (max)/PD  
For aluminum electrolytic capacitors, ESR will increase by  
about 30X as the temperature is reduced from 25°C to −40°  
C. This type of capacitor is not well-suited for low temperature  
operation.  
IMPORTANT: If the maximum allowable value for θ(JA) is  
found to be 60°C/W for the TO-220 package, 80°C/W for  
the TO-263 package, or 174°C/W for the SOT-223 package,  
no heatsink is needed since the package alone will dissipate  
enough heat to satisfy these requirements.  
Solid tantalum capacitors have a more stable ESR over tem-  
perature, but are more expensive than aluminum electrolyt-  
ics. A cost-effective approach sometimes used is to parallel  
an aluminum electrolytic with a solid Tantalum, with the total  
capacitance split about 75/25% with the Aluminum being the  
larger value.  
If the calculated value for θ(JA)falls below these limits, a  
heatsink is required.  
HEATSINKING TO-220 PACKAGE PARTS  
The TO-220 can be attached to a typical heatsink, or secured  
to a copper plane on a PC board. If a copper plane is to be  
used, the values of θ(JA) will be the same as shown in the next  
section for the TO-263.  
If two capacitors are paralleled, the effective ESR is the par-  
allel of the two individual values. The “flatter” ESR of the  
Tantalum will keep the effective ESR from rising as quickly at  
low temperatures.  
www.national.com  
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