dershoot. This usually happens when the load toggles high at
the time VOUT just ramps down to its regulation level from an
overshoot. Figure 4 shows such a case where the load tog-
gles between 1.7A and only 50mA.
The recommended voltage for the external bias is 5V. Due to
the absolute maximum rating of VBST - VSW, the external 5V
bias should not be higher than 6V.
THERMAL SHUTDOWN
Whenever the junction temperature of the LM26400Y ex-
ceeds 165°C, the MOSFET switch will be kept off until the
temperature drops below 150°C, at which point the regulator
will go through a hard-start to quickly raise the output voltage
back to normal. Since it is a hard-start, there will be an over-
shoot at the output. See Thermal Shutdown in the Typical
Performance Characteristics section.
POWER LOSS ESTIMATION
The total power loss in the LM26400Y comprises of three
parts - the power FET conduction loss, the power FET switch-
ing loss and the IC's housekeeping power loss. Use the
following equation to estimate the conduction loss.
where TJ is the junction temperature or the target junction
temperature if the former is unknown. RDS is the ON resis-
tance of the internal FET at room temperature. Use 180mΩ
for RDS if the actual value is unknown.
20200241
FIGURE 4. Extreme Load Step
In the example, the load first goes down to 50mA quickly
(0.9A/µs), causing a 90µs no-switching period, and then
quickly goes up to 1.7A when VOUT1 just hits its regulation
level (1.2V), resulting in a large dip of 440mV in the output
voltage.
Use the following equation to estimate the switching loss.
Another loss in the IC is the housekeeping loss. It is the power
dissipated by circuitry in the IC other than the power FETs.
The equation is:
If it is known in a system design that the load can go down to
less than 100mA during a load step, and that the load can
toggle high any time after it toggles low, take the following
measures to minimize the potential extra undershoot. First is
to add the Cff mentioned above. Second is to increase the
output capacitance.
The 15mW is gate drive loss. Do the calculation for both
channels and find out the total power loss in the IC.
For example, to meet a ±10% VOUT excursion requirement for
a 100mA to 2A load step, approximately 200µF output ca-
pacitance is needed for a 1.2V output, and about 44µF is
needed for a 5V output.
LOW INPUT VOLTAGE CONSIDERATIONS
The power loss calculation can help estimate the overall pow-
er supply efficiency.
When VIN is between 3V and 5V, it is recommended that an
external bootstrap bias voltage and a Schottky diode be used
to handle load currents up to 2A. See Figure 5 for an illustra-
tion.
Example:
VIN = 12V, VOUT1 = 1.2V, IOUT1 = 2A, VOUT2 = 2.5V, IOUT2 = 2A.
Target junction temperature is 90°C.
So conduction loss in Channel 1 is:
Conduction loss in Channel 2 is:
Switching loss in either channel is:
20200244
FIGURE 5. External Bootstrap for Low VIN
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