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LM2639M 参数 Datasheet PDF下载

LM2639M图片预览
型号: LM2639M
PDF下载: 下载PDF文件 查看货源
内容描述: 5位可编程,高频多相PWM控制器 [5-Bit Programmable, High Frequency Multi-phase PWM Controller]
分类和应用: 开关控制器
文件页数/大小: 9 页 / 150 K
品牌: NSC [ National Semiconductor ]
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Pin Description  
Pin  
1
Pin Name  
Vcc5V  
Pin Function  
Supply Voltage Input (5V nominal)  
2
Divsel  
Selects Phase Mode. Logic low selects 4 phase. Logic high selects 3 phase. 2 phase  
operation is achieved by using 2 outputs in 4 phase mode.  
3
4
Clksel  
Extclk  
Clock Select: Logic high selects internal clock. Logic low selects external clock.  
=
External Clock Input. Output frequency Clock Input / No. of Phases. Connect to Vcc5V to  
select internal clock.  
5
Rref  
Connects to external reference resistor. Sets the operating frequency of the internal clock  
and the ramp time for the PWM. Reference voltage at this pin is 1.26V.  
6
7
Vid0  
Vid1  
Vid2  
Vid3  
Vid4  
OC+  
OC−  
COMP  
5-Bit DAC Input (LSB).  
5-Bit DAC Input.  
8
5-Bit DAC Input.  
9
5-Bit DAC Input.  
10  
11  
12  
13  
5-Bit DAC Input (MSB)  
Over-current Comparator. Non-inverting input.  
Over-current Comparator. Inverting input.  
Compensation Pin. This is the output of the internal transconductance amplifier.  
Compensation network should be connected between this pin and feedback ground FBG.  
14  
15  
FB  
Feedback Input. Normally Kelvin connected to supply output.  
Bgout  
Current Limit Flag. Goes to logic low when current limit is activated. When over-current  
condition is removed, this pin is weakly pulled up to Vcc5V.  
16  
17  
18  
19  
20  
21  
22  
23  
24  
FBG  
Feedback Ground. This pin should be connected to the ground at the supply output.  
ENABLE  
GND  
Output Enable Pin. Tie to logic high to enable and logic low to disable.  
Power Ground Pin.  
DRV2  
DRV0  
Vcc12V  
DRV1  
DRV3  
OutV  
Phase 2 Output.  
Phase 0 Output.  
Supply Voltage for FET Drivers DRV0:3.  
Phase 1 Output.  
Phase 3 Output.  
Sets the maximum DRV0:3 drive voltage to reduce switching loss in external FET’s.  
5
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