LM2622
Operation
(Continued)
very little load changes, and at lower current outputs, the
input capacitor size can often be reduced. The size can also
be reduced if the input of the regulator is very close to the
source output. The size will generally need to be larger for
applications where the regulator is supplying nearly the
maximum rated output or if large load steps are expected. A
minimum value of 10µF should be used for the less stressful
condtions while a 22µF to 47µF capacitor may be required
for higher power and dynamic loads. Larger values and/or
lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted R
ESR
) capacitors be used such as
ceramic, polymer electrolytic, or low ESR tantalum. Higher
ESR capacitors may be used but will require more compen-
sation which will be explained later on in the section. The
ESR is also important because it determines the peak to
peak output voltage ripple according to the approximate
equation:
∆V
OUT
)
2∆i
L
R
ESR
(in Volts)
A minimum value of 10µF is recommended and may be
increased to a larger value. After choosing the output capaci-
tor you can determine a pole-zero pair introduced into the
control loop by the following equations:
given in the
Introduction to Compensation
section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
where R
O
is the output impedance of the error amplifier,
approximately 1MegΩ. Since R
C
is generally much less than
R
O
, it does not have much effect on the above equation and
can be neglected until a value is chosen to set the zero f
ZC
.
f
ZC
is created to cancel out the pole created by the output
capacitor, f
P1
. The output capacitor pole will shift with differ-
ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of f
P1
over the ex-
pected loads and then set the zero f
ZC
to a point approxi-
mately in the middle. The frequency of this zero is deter-
mined by:
Where R
L
is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the
High
Output Capacitor ESR Compensation
section.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90˚ in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than
1
⁄
2
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
Now R
C
can be chosen with the selected value for C
C
.
Check to make sure that the pole f
PC
is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if
desired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R
C
should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran-
sients. If more detail is required, or the most optimal perfor-
mance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
C2
, directly from the compensation pin V
C
to ground, in
parallel with the series combination of R
C
and C
C
. The pole
should be placed at the same frequency as f
Z1
, the ESR
zero. The equation for this pole follows:
To ensure this equation is valid, and that C
C2
can be used
without negatively impacting the effects of R
C
and C
C
, f
PC2
must be greater than 10f
ZC
.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a
bandwidth of
1
⁄
2
or less of the frequency of the RHP zero.
This is done by calculating the open-loop DC gain, A
DC
. After
this value is known, you can calculate the crossover visually
by placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than
1
⁄
2
the RHP zero, the phase
margin should be high enough for stability. The phase mar-
10
where I
LOAD
is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
C
and C
C
is to set a dominant low frequency pole in the control
loop. Simply choose values for R
C
and C
C
within the ranges
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