Application Circuits
A typical ground fault interrupter circuit is shown in
Figure 2
It is designed to operate on 120 V
AC
line voltage with 5 mA
normal fault sensitivity
A full-wave rectifier bridge and a 15k 2W resistor are used
to supply the DC power required by the IC A 1
mF
capacitor
at pin 8 used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle When a fault causes the SCR to trigger
the circuit breaker is energized and line voltage is removed
from the load At this time no fault current flows and the IC
discharge current increases from I
TH
to 3I
TH
(see Circuit
Description and Block Diagram) This quickly resets both
the timing capacitor and the output latch At this time the
circuit breaker can be reset and the line voltage again sup-
plied to the load assuming the fault has been removed A
1000 1 sense transformer is used to detect the normal fault
The fault current which is basically the difference current
between the hot and neutral lines is stepped down by 1000
and fed into the input pins of the operational amplifier
through a 10
mF
capacitor The 0 0033
mF
capacitor be-
tween pin 2 and pin 3 and the 200 pF between pins 3 and 4
are added to obtain better noise immunity The normal fault
sensitivity is determined by the timing capacitor discharging
current I
TH
I
TH
can be calculated by
7V
d
2
(1)
I
TH
e
R
SET
At the decision point the average fault current just equals
the threshold current I
TH
I
f(rms)
c
0 91
(2)
I
TH
e
2
where I
f(rms)
is the rms input fault current to the operational
amp and the factor of 2 is due to the fact that I
f
charges the
timing capacitor only during one half-cycle while I
TH
dis-
charges the capacitor continuously The factor 0 91 con-
verts the rms value to an average value Combining equa-
tions (1) and (2) we have
(3)
I
f(rms)
c
0 91
For example to obtain 5 mA(rms) sensitivity for the circuit in
Figure 2
we have
7V
e
1 5M
X
(4)
R
SET
e
5 mA
c
0 91
1000
The correct value for R
SET
can also be determined from the
characteristic curve that plots equation (3) Note that this is
an approximate calculation the exact value of R
SET
de-
pends on the specific sense transformer used and LM1851
tolerances Inasmuch as UL943 specifies a sensitivity ‘‘win-
dow’’ of 4 mA–6 mA provision should be made to adjust
R
SET
on a per-product basis
Independent of setting sensitivity the desired integration
time can be obtained through proper selection of the timing
capacitor C
t
Due to the large number of variables involved
proper selection of C
t
is best done empirically The following
design example then should only be used as a guideline
Assume the goal is to meet UL943 timing requirements
Also assume that worst case timing occurs during GF1
R
SET
e
7V
start-up (S1 closure) with both a heavy normal fault and a
2X grounded neutral fault present This situation is shown dia-
gramatically below
TL H 5177 – 5
UL943 specifies
s
25 ms average trip time under these con-
ditions Calculation of C
t
based upon charging currents due
to normal fault only is as follows
s
25 ms Specification
b
3 ms GFI turn-on time (15k and 1
mF)
b
8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
b
4 ms Time required to open a sluggish circuit breaker
s
10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates com-
ponent tolerances and other variables
I
c
T
V
where T
e
integration time
V
e
threshold voltage
C
t
e
I
e
average fault current into C
t
I
e
(5)
X
120 V
AC(rms)
R
B
J
Y
c
X
R
R
N
G
a
R
N
Y
J
heavy fault
current generated
(swamps I
TH
)
portion of
fault current
shunted
around GFI
c
c
X
1 turn
1000 turns
J
Y
c
J
X Y
1
2
C
t
charging
on half-
cycles only
(0 91)
(6)
X Y
rms to
average
conversion
current
division of
input sense
transformer
therefore
C
t
e
C
t
e
500
J
1 6
120
c
04
a
0 4
J
1000
J
2
J
c
1
c
1
c
(0 91)
17 5
(
c
0 0008
(7)
0 01
mF
5
NSC [ NATIONAL SEMICONDUCTOR ]
