Deserializer Pin Description (Continued)
Pin Name
RCLK_R/F
I/O
No.
Description
I
2
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
RI+
I
I
I
5
6
7
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
RI−
PWRDN
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL.
LOCK
O
10
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
RCLK
REN
O
I
9
8
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
DVCC
DGND
AVCC
I
I
I
I
I
21, 23
14, 20, 22
4, 11
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
AGND
REFCLK
1, 12, 13
3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
Truth Table
RI
X
RI−
X
RCLK_R/F
REFCLK
REN
PWRDN
RCLK
Z
LOCK
ROUT (0–9)
X
X
X
X
X
1
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
X
X
0
0
1
1
1
0
X
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
→
DATA (0–9)
DATA (0–9)
SYNC PTRN
DATA (0–9)
DATA (0–9)
* Inverted
DATA (0–9)*
DATA (0–9)*
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
Z
L
Z **
Z
Z
→
Z
H
PLL **
CLK
L
K
1
0
0
SYNC PTRN
DATA
0
DATA
**If the Rx is locked when REN goes low the LOCK* output will go Tri-state on the rising edge of REFCLK. If the Rx is not locked when REN goes low the LOCK*
output will remain active. It will be high as the Rx is not locked but should the Rx attain lock the LOCK* output will go low to indicate lock.
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