Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
tRCP
Receiver out Clock
Period
Figure 3
tRCP = tTCP
RCLK
25
62.5
ns
tCLH
tCHL
tDD
CMOS/TTL Low-to-High
Transition Time
CL = 15 pF
Figure 2
Rout(0-9),
1.2
1.1
4
4
ns
CMOS/TTL High-to-Low
Transition Time
LOCK, RCLK
ns
ns
Deserializer Delay
Figure 4
All Temp./All Freq. 1.75*tRCP+ 1.25 1.75*tRCP+3.75 1.75*tRCP+6.25
Room Temp
1.75*tRCP+ 2.25 1.75*tRCP+3.75 1.75*tRCP+5.25
3.3V/40MHz
tROS
tROH
ROUT (0-9) Setup Data to Figure 5
RCLK
RCLK
0.4*tRCP
0.5*tRCP
ns
ns
ROUT (0-9) Hold Data to
RCLK
−0.4*tRCP
45
−0.5*tRCP
tRDC
tHZR
tLZR
RCLK Duty Cycle
50
55
%
ns
ns
ns
ns
HIGH to TRI-STATE Delay Figure 6
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer PLL Lock Time Figure 7
Rout(0-9),
LOCK
4.2+0.5*tRCP
4.5+0.5*tRCP
6+0.5*tRCP
6.0+0.5*tRCP
10+tRCP
10+tRCP
12+tRCP
12+tRCP
tZHR
tZLR
tDSR1
16MHz
40MHz
4
10
3
µs
µs
from PWRDWN (with
SYNCPAT)
Figure 8
(Note 4)
1.31
tDSR2
Deserializer PLL Lock time
from SYNCPAT
16MHz
40MHz
1.2
5
1
µs
µs
0.47
tZHLK
tRNM
TRI-STATE to HIGH Delay
(Power-up)
LOCK
4.62
12
ns
Deserializer Noise Margin
Figure 9
(Note 5)
16 MHz
40 MHz
900
450
1100
730
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH
and VTL which are differential voltages.
Note 4: For the purpose of specifying Deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the Deserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time required
for the Deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before initiating
either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled Deserializer when the input (RI+ and RI-) conditions change from not
receiving data to receiving synchronization patterns (SYNCPATs).
Note 5: tRNM is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur.
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