Parameter Measurement Information
(Continued)
DS100888-5
C
L
includes load and test jig capacitance.
S
1
= V
CC
for t
PZL
and t
PLZ
measurements.
S
1
= GND for t
PZH
and t
PHZ
measurements.
FIGURE 3. Receiver TRI-STATE Delay Test Circuit
DS100888-6
FIGURE 4. Receiver TRI-STATE Delay Waveforms
Typical Application
Balanced System
DS100888-7
FIGURE 5. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 5.
This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic impedance of
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4
the media is in the range of 100Ω. A termination resistor of
100Ω (selected to match the media), and is located as close
to the receiver input pins as possible. The termination resis-
tor converts the driver output (current mode) into a voltage
that is detected by the receiver. Other configurations are
possible such as a multi-receiver configuration, but the ef-
fects of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken
into account.
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