DS90LV048A
Applications Information
(Continued)
gin (+25mV − (−35mV)). With the enhanced threshold region
of −100mV to 0V, this small external fail-safe biasing of
+25mV (with respect to 0V) gives a DNM of a comfortable
60mV. With the standard threshold region of
±
100mV, the
external fail-safe biasing would need to be +25mV with
respect to +100mV or +125mV, giving a DNM of 160mV
which is stronger fail-safe biasing than is necessary for the
DS90LV048A. If more DNM is required, then a stronger
fail-safe bias point can be set by changing resistor values.
10088830
FIGURE 6. VTC of the DS90LV048A LVDS Receiver
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1.
Open Input Pins.
The DS90LV048A is a quad receiver
device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2.
Terminated Input.
If the driver is disconnected (cable
unplugged), or if the driver is in a TRI-STATE or power-
off condition, the receiver output will again be in a HIGH
state, even with the end of cable 100Ω termination re-
sistor across the input pins. The unplugged cable can
become a floating antenna which can pick up noise. If
the cable picks up more than 10mV of differential noise,
the receiver may see the noise as a valid signal and
switch. To insure that any noise is seen as common-
mode and not differential, a balanced interconnect
should be used. Twisted pair cable will offer better bal-
ance than flat ribbon cable.
3.
Shorted Inputs.
If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
Additional information on fail-safe biasing of LVDS devices
may be found in AN-1194.
Pin Descriptions
Pin No.
2, 3, 6, 7
1, 4, 5, 8
10, 11, 14,
15
16
EN
Receiver enable pin: When EN is
low, the receiver is disabled.
When EN is high and EN* is low
or open, the receiver is enabled. If
both EN and EN* are open circuit,
then the receiver is disabled.
Receiver enable pin: When EN* is
high, the receiver is disabled.
When EN* is low or open and EN
is high, the receiver is enabled. If
both EN and EN* are open circuit,
then the receiver is disabled.
Power supply pin, +3.3V
±
0.3V
Ground pin
Name
R
IN+
R
IN−
R
OUT
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
9
EN*
13
12
V
CC
GND
Ordering Information
Operating
Temperature
−40˚C to +85˚C
−40˚C to +85˚C
Package Type/
Number
SOP/M16A
TSSOP/MTC16
DS90LV048ATM
DS90LV048ATMTC
Order Number
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