DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
August 2005
DS90LV018A
3V LVDS Single CMOS Differential Line Receiver
General Description
The DS90LV018A is a single CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV018A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS
output levels. The receiver also supports open, shorted and
terminated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV018A has a
flow-through design for easy PCB layout.
The DS90LV018A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
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400 Mbps (200 MHz) switching rates
50 ps differential skew (typical)
2.5 ns maximum propagation delay
3.3V power supply design
Flow-through pinout
Power down high impedance on LVDS inputs
Low Power design (18mW
@
3.3V static)
Interoperable with existing 5V LVDS networks
Accepts small swing (350 mV typical) differential signal
levels
Supports open, short and terminated input fail-safe
Conforms to ANSI/TIA/EIA-644 Standard
Industrial temperature operating range
(−40˚C to +85˚C)
Available in SOIC package
Connection Diagram
SOIC
Truth Table
INPUTS
[R
IN
+] − [R
IN
−]
V
ID
≥
0.1V
V
ID
≤
−0.1V
Full Fail-safe
OPEN/SHORT
10007801
OUTPUT
R
OUT
H
L
H
or Terminated
Order Number DS90LV018ATM
See NS Package Number M08A
Functional Diagram
10007802
© 2005 National Semiconductor Corporation
DS100078
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
