AC Timing Diagrams (Continued)
DS100871-20
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typicaIIy 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 75MHz
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 17. Receiver LVDS Input Skew Margin
Applications Information
The DS90CR217 and DS90CR218 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V
system the following must be addressed:
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled wilI lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL V
.
CC
DS90CR217 Pin Description— Channel Link Transmitter
Pin Name
TxIN
I/O
I
No.
21
3
Description
TTL level input.
TxOUT+
O
O
I
Positive LVDS differential data output.
Negative LVDS differential data output.
TxOUT−
3
TxCLK IN
1
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
TxCLK OUT+
TxCLK OUT−
PWR DWN
O
O
I
1
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at
power down.
V CC
I
I
I
I
I
I
4
5
1
2
1
3
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pins for PLL.
Ground pins for PLL.
GND
PLL V CC
PLL GND
LVDS V CC
LVDS GND
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90CR218 Pin Description— Channel Link Receiver
Pin Name
RxIN+
I/O
No.
3
Description
Positive LVDS differential data inputs. (Note 12)
I
I
RxIN−
3
Negative LVDS differential data inputs. (Note 12)
TTL level data outputs.
RxOUT
O
I
21
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
11
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