DS90CF561 Pin Description — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
O
O
I
O
O
I
I
I
I
I
I
I
No.
21
3
3
1
1
1
1
4
5
1
2
1
3
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME,
DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The falling edge acts as data strobe.
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
DS90CF562 Pin Description — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
I
O
I
I
O
I
I
I
I
I
I
I
No.
3
3
21
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The falling edge acts as data strobe.
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
Description
11
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
