DS90CF363A Pin Description — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
O
O
I
O
O
I
I
I
I
I
I
I
No.
21
3
3
1
1
1
1
4
4
1
2
1
3
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Applications Information
The DS90C363A/DS90CF363A are backward compatible
with the DS90C363/DS90CF363 and are a pin-for-pin re-
placement. The device (DS90C363A/DS90CF363A) utilizes
a different PLL architecture employing an internal 7X clock
for enhanced pulse position control.
This device (DS90C363A/DS90CF363A) also features re-
duced variation of the TCCD parameter which is important
for dual pixel applications. (See AN-1084) TCCD variation
has been measured to be less than 250ps at 65MHz under
normal operating conditions.
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the V
CC
, LVDS V
CC
and PLL V
CC
of the transmitter.
2. The DS90C363A transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
3. To implement a falling edge device for the DS90C363A,
the R_FB pin (pin 14) may be tied to ground OR left un-
connected (an internal pull-down resistor biases this pin
low). Biasing this pin to Vcc implements a rising edge
device.
Transmitter Clock Jitter Cycle-to-Cycle
Figures 12 and 13 illustrate the timing of the input clock rela-
tive to the input data. The input clock (TxCLKin) is intention-
ally shifted to the left −3ns and +3ns to the right when data
(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-
peated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-to-
cycle jitter at 2µs period.
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