DS14C335
Parameter Measurement Information
(Continued)
DS011734-8
FIGURE 6. Driver SHUTDOWN (SD) Delay Timing
DS011734-9
FIGURE 7. Receiver SHUTDOWN (SD) Delay Test Circuit
DS011734-10
FIGURE 8. Receiver SHUTDOWN (SD) Delay Timing
Pin Descriptions
V
CC
(Pin 3).
Power supply pin for the device, +3.3V (
±
0.3V).
V+ (Pin 1).
Positive supply for TIA/EIA-232-E drivers. Rec-
ommended external capacitor — 0.47 µF (16V). This supply
is not intended to be loaded externally.
V− (Pin 25).
Negative supply for TIA/EIA-232-E drivers. Rec-
ommended external capacitor — 0.47 µF (16V). This supply
is not intended to be loaded externally.
C1+, C1− (Pins 6, 24).
External capacitor connection pins.
Recommended capacitor — 0.47 µF (6.3V).
C2+, C2− (Pins 2, 4).
External capacitor connection pins.
Recommended capacitor — 0.47 µF (16V).
C3+, C3− (Pins 28, 26).
External capacitor connection pins.
Recommended capacitor — 0.47 µF (6.3V).
SHUTDOWN (SD) (Pin 23).
A High on the SHUTDOWN pin
will lower the total I
CC
current to less than 10 µA, providing a
low power state. In this mode receiver R5 remains active.
The SD pin should be driven or tied low (GND) to disable the
shutdown mode.
D
IN
1–3 (Pins 7, 8, 9).
Driver input pins are JEDEC 3.3V
standard compatible.
D
OUT
1–3 (Pins 22, 21, 20).
Driver output pins conform to
TIA/ElA-232 -E levels.
R
IN
1–5 (Pins 19, 18, 17, 16, 15).
Receiver input pins accept
TIA/EIA-232-E input voltages (
±
25V). Receivers guarantees
hysteresis of TBD mV. Unused receiver input pins may be
left open. Internal input resistor (5 kΩ) pulls input LOW, pro-
viding a failsafe HIGH output.
R
OUT
1–5 (Pins 10, 11, 12, 13, 14).
Receiver output pins are
JEDEC 3.3V standard compatible.
GND (Pin 27).
Ground Pin.
5
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