6 0 Pin Descriptions
(Continued)
For the PLCC packaged DP8392 it is recommended that a
small printed circuit board V
EE
plane be connected to pins
5– 11 and a second one be connected to pins 20–25 To
reduce the thermal resistance to the required value the
area of the plane on EACH set of pins should be
t
0 20 in
2
for applications with low transmitter duty cycle and
t
0 4 in
2
for high transmit duty cycle applications
Figure 7
illustrates
a recommended component side layout for these planes
TL F 11085 – 14
Layout as viewed from component side
FIGURE 6 Typical Layout Considerations
for DP8392CN
(Not to Scale)
TL F 11085 – 15
FIGURE 7 Recommended Layout and Dissipation Planes for DP8392CV (Not to Scale)
6
NSC [ NATIONAL SEMICONDUCTOR ]
