欢迎访问ic37.com |
会员登录 免费注册
发布采购

DP83902AVLJ 参数 Datasheet PDF下载

DP83902AVLJ图片预览
型号: DP83902AVLJ
PDF下载: 下载PDF文件 查看货源
内容描述: ST- NICTM串行网络接口控制器,用于双绞线 [ST-NICTM Serial Network Interface Controller for Twisted Pair]
分类和应用: 网络接口外围集成电路数据传输控制器局域网时钟
文件页数/大小: 70 页 / 848 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
 浏览型号DP83902AVLJ的Datasheet PDF文件第2页浏览型号DP83902AVLJ的Datasheet PDF文件第3页浏览型号DP83902AVLJ的Datasheet PDF文件第4页浏览型号DP83902AVLJ的Datasheet PDF文件第5页浏览型号DP83902AVLJ的Datasheet PDF文件第6页浏览型号DP83902AVLJ的Datasheet PDF文件第7页浏览型号DP83902AVLJ的Datasheet PDF文件第8页浏览型号DP83902AVLJ的Datasheet PDF文件第9页  
DP83902A ST-NIC Serial Network Interface Controller for Twisted Pair
PRELIMINARY
November 1995
DP83902A ST-NIC
TM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA CD local area net-
works These include Ethernet (10BASE5) Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T) The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface
and 10BASE-T transceiver functions in accordance with the
IEEE 802 3 standards
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard This functional block incorporates the
receiver transmitter collision heartbeat loopback jabber
and link integrity blocks as defined in the standard The
transceiver when combined with equalization resistors
transmit receive filters and pulse transformers provides a
complete physical interface from the DP83902A’s ENDEC
module and the twisted pair medium
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit sec Also included are colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
(Continued)
Features
Single chip solution for IEEE 802 3 10BASE-T
Integrated controller ENDEC and transceiver
Y
Full AUI interface
Y
No external precision components required
Y
3 levels of loopback supported
Transceiver Module
Y
Integrates transceiver electronics including
Transmitter and receiver
Collision detect heartbeat and jabber timer
Link integrity test
Y
Link disable and polarity detection correction
Y
Integrated smart receive squelch
Y
Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y
10 Mb s Manchester encoding decoding plus clock re-
covery
Y
Transmitter half or full step mode
Y
Squelch on receive and collision pairs
Y
Lock time 5 bits typical
Y
Decodes Manchester data with up to
g
18 ns jitter
MAC Controller Module
Y
100% DP8390 software hardware compatible
Y
Dual 16-bit DMA channels
Y
16-byte internal FIFO
Y
Efficient buffer management implementation
Y
Independent system and network clocks
Y
Supports physical multicast and broadcast address fil-
tering
Y
Network statistics storage
Y
Y
1 0 System Diagram
Station or DTE
TL F 11157 –1
TRI-STATE is a registered trademark of National Semiconductor Corporation
ST-NIC
TM
is a trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 11157
RRD-B30M115 Printed in U S A