8.0 USART (Continued)
DS101116-41
FIGURE 24. USART BAUD Clock Generation
DS101116-42
FIGURE 25. USART BAUD Clock Divisor Registers
TABLE 4. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Prescaler
Select
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Prescaler
Factor
4.5
5
Baud
Rate
Baud Rate
Divisor − 1
(N-1)
5.5
6
110
1046
(110.03)
6.5
7
134.5
855
(134.58)
7.5
8
150
300
767
383
191
95
63
47
31
23
15
11
5
8.5
9
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
9.5
10
10.5
11
11.5
12
12.5
13
2
13.5
14
Note: The entries in Table 5 assume a prescaler output of 1.8432 MHz. In the
asynchronous mode the baud rate could be as high as 987.5k.
14.5
15
TABLE 5. Prescaler Factors
Prescaler
Select
00000
00001
00010
00011
00100
00101
00110
00111
Prescaler
15.5
16
Factor
NO CLOCK
1
1.5
2
2.5
3
3.5
4
29
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