Table of Contents (Continued)
12.1.1 ITMR Register .................................................................................................................................. 31
12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 31
12.2.1 Timer Operating Speeds .................................................................................................................. 31
12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 31
12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 32
12.2.4 Mode 3. Input Capture Mode .......................................................................................................... 32
12.3 TIMER CONTROL FLAGS .................................................................................................................... 33
12.4 TIMER T2 OPERATION IN IDLE MODE .............................................................................................. 35
12.4.1 Timer T2 Clocking Scheme ............................................................................................................. 35
13.0 Power Saving Features ............................................................................................................................ 36
13.1 POWER SAVE MODE CONTROL REGISTER .................................................................................... 36
13.2 OSCILLATOR STABILIZATION ............................................................................................................. 37
13.3 HIGH SPEED MODE OPERATION ...................................................................................................... 37
13.3.1 High Speed Halt Mode .................................................................................................................... 37
13.3.1.1 Entering The High Speed Halt Mode ......................................................................................... 37
13.3.1.2 Exiting The High Speed Halt Mode ........................................................................................... 37
13.3.1.3 HALT Exit Using Reset .............................................................................................................. 37
13.3.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 37
13.3.1.5 Options ....................................................................................................................................... 38
13.3.2 High Speed Idle Mode ..................................................................................................................... 38
13.4 DUAL CLOCK MODE OPERATION ...................................................................................................... 39
13.4.1 Dual Clock HALT Mode ................................................................................................................... 39
13.4.1.1 Entering The Dual Clock Halt Mode .......................................................................................... 39
13.4.1.2 Exiting The Dual Clock Halt Mode ............................................................................................. 39
13.4.1.3 HALT Exit Using Reset .............................................................................................................. 39
13.4.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 39
13.4.1.5 Options ....................................................................................................................................... 39
13.4.2 Dual Clock Idle Mode ...................................................................................................................... 39
13.5 LOW SPEED MODE OPERATION ....................................................................................................... 40
13.5.1 Low Speed HALT Mode ................................................................................................................... 40
13.5.1.1 Entering The Low Speed Halt Mode ......................................................................................... 40
13.5.1.2 Exiting The Low Speed Halt Mode ............................................................................................ 40
13.5.1.3 HALT Exit Using Reset .............................................................................................................. 40
13.5.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 40
13.5.1.5 Options ....................................................................................................................................... 40
13.5.2 Low Speed Idle Mode ...................................................................................................................... 41
13.6 MULTI-INPUT WAKE-UP ...................................................................................................................... 42
14.0 USART ..................................................................................................................................................... 42
14.1 USART CONTROL AND STATUS REGISTERS ................................................................................... 43
14.2 DESCRIPTION OF USART REGISTER BITS ...................................................................................... 43
14.3 ASSOCIATED I/O PINS ........................................................................................................................ 44
14.4 USART OPERATION ............................................................................................................................ 45
14.4.1 Asynchronous Mode ........................................................................................................................ 45
14.4.2 Synchronous Mode .......................................................................................................................... 45
14.5 FRAMING FORMATS ............................................................................................................................ 45
14.6 USART INTERRUPTS .......................................................................................................................... 46
14.7 BAUD CLOCK GENERATION .............................................................................................................. 46
14.8 EFFECT OF HALT/IDLE ....................................................................................................................... 48
14.9 DIAGNOSTIC ........................................................................................................................................ 48
14.10 ATTENTION MODE ............................................................................................................................. 48
14.11 BREAK GENERATION ........................................................................................................................ 48
15.0 A/D Converter ........................................................................................................................................... 49
15.1 9.1 OPERATING MODES ..................................................................................................................... 49
15.1.1 A/D Control Register ........................................................................................................................ 49
15.1.1.1 Channel Select ........................................................................................................................... 49
15.1.1.2 Multiplexor Output Select ........................................................................................................... 50
15.1.1.3 Mode Select ............................................................................................................................... 51
15.1.1.4 Prescaler Select ......................................................................................................................... 51
15.1.1.5 Busy Bit ...................................................................................................................................... 51
15.1.2 A/D Result Registers ....................................................................................................................... 51
15.2 PROGRAMMABLE GAIN AMPLIFIER .................................................................................................. 52
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NSC [ National Semiconductor ]
