Input Interfacing
The CLC014 accepts either differential or single-ended input
voltage specified in
Static Performance
. The following sec-
tions show several suggestions for interfaces for the inputs
and outputs of the CLC014.
SINGLE-ENDED INPUT INTERFACE: 75Ω Coaxial Cable
The input is connected single-ended to either DI or DI as
shown in
Figure 3.
Balancing unused inputs helps to lessen
the effects of noise. Use the equivalent termination of 37.5Ω
to balance the input impedance seen by each pin. It also
helps to terminate grounds at a common point. Resistors R
x
and R
y
are recommended for optimum performance. The
equalizer inputs are self-biasing. Signals should be AC
coupled to the inputs as shown in
Figure 3.
DO and DO pins are
not complementary emitter coupled
logic
outputs. Instead, the outputs are taken off of the collec-
tors of the transistors. Therefore, care must be taken to meet
the interface threshold levels required by ECL families. Rec-
ommended interfaces for standard ECL families are shown
in the following circuits.
DIFFERENTIAL LOAD-TERMINATED OUTPUT
INTERFACE
Figure 5
shows a recommended circuit for implementing a
differential output that is terminated at the load. A diode or
75Ω resistor provides a voltage drop from the positive supply
(+5V for PECL or Ground for ECL operation) to establish
proper ECL levels. The resistors terminate the cable to the
characteristic impedance. The output voltage swing is deter-
mined by the CLC014 output current (10 mA) times the ter-
mination resistor. For the circuit in
Figure 5,
the nominal out-
put voltage swing is 750 mV.
DS100056-22
FIGURE 3. Single-Ended 75Ω Cable Input Interface
DIFFERENTIAL INPUT INTERFACE: Twisted Pair
A recommended differential input interface is shown in
Fig-
ure 4.
Proper voltage levels must be furnished to the input
pins and the proper cable terminating impedance must be
provided. For Category 5 UTP this is approximately 100Ω.
Figure 4
shows a generalized network which may be used to
receive data over a twisted pair. Resistors R
1
and R
2
provide
the proper terminating impedance and signal level adjust-
ment. The blocking capacitors provide AC coupling of the at-
tenuated signal levels. The plots in the
Typical Perfor-
mance Characteristics
section demonstrate various
equalized data rates using Category 5 UTP at 100 meter
lengths. A full schematic of a recommended driver and re-
ceiver circuit for 100Ω Category 5 UTP is provided in the
Typical Applications
section with further explanation.
DS100056-25
FIGURE 5. Differential Load Terminated
Output Interface
DIFFERENTIAL SOURCE-TERMINATED OUTPUT
INTERFACE
Figure 6
is similar to
Figure 5
except that the termination is
provided at the source. This configuration may also be used
for single-ended applications. However, the unused output
must still be terminated as shown.
DS100056-26
FIGURE 6. Differential Source Terminated
Output Interface
DS100056-24
FIGURE 4. Twisted Pair Input Interface
Output Interfacing
The outputs DO and DO produce ECL logic levels when the
recommended output termination networks are used. The
9
TERMINATING PHYSICALLY SEPARATED OUTPUTS
When the two outputs must be routed to physically separate
locations, the circuit in
Figure 6
may be applied. Alterna-
tively, if load termination is desired, the circuit in
Figure 7
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