Functional Description (Continued)
TABLE 6. MUX Addressing: ADC0832
Single-Ended MUX Mode
MUX Address Channel #
SGL/
DIF
1
ODD/
SIGN
0
0
1
+
1
1
+
COM is internally tied to A GND
TABLE 7. MUX Addressing: ADC0832
Differential MUX Mode
MUX Address
Channel #
SGL/
DIF
0
ODD/
SIGN
0
0
1
+
−
−
+
0
1
Since the input configuration is under software control, it can
be modified, as required, at each conversion. A channel can
be treated as a single-ended, ground referenced input for
one conversion; then it can be reconfigured as part of a dif-
ferential channel for another conversion. Figure 1 illustrates
the input flexibility which can be achieved.
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting
highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above VCC (typically 5V) with-
out degrading conversion accuracy.
1. A conversion is initiated by first pulling the CS (chip select)
line low. This line must be held low for the entire conversion.
The converter is now waiting for a start bit and its MUX as-
signment word.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows more function to be included in the
2. A clock is then generated by the processor (if not provided
continuously) and output to the A/D clock input.
www.national.com
14
NSC [ National Semiconductor ]
