Switching Characteristics
5.0V, T
e a
e a
25 C (See Section 1 for waveforms and load configurations)
V
CC
§
A
e
C
L
15 pF
Symbol
Parameter
Units
Min
Max
t
t
Propagation Delay
e
14
14
PLH
PHL
ns
ns
ns
ns
E to A
B
t
t
Propagation Delay
l
25
22
PLH
PHL
A , B to A
n n
B
t
t
Propagation Delay
k
26
21
PLH
PHL
A , B to A
n n
B
t
t
Propagation Delay
e
30
32
PLH
PHL
A , B to A
n n
B
Functional Description
Truth Table
The ’24 5-bit comparators use combinational circuitry to di-
rectly generate ‘‘A greater than B’’ and ‘‘A less than B’’
outputs. As evident from the logic diagram, these outputs
are generated in only three gate delays. The ‘‘A equals B’’
output is generated in one additional gate delay by decoding
the ‘‘A neither less than nor greater than B’’ condition with a
NOR gate. All three outputs are activated by the active LOW
Enable Input (E).
Inputs
Outputs
k
l
e
E
A
n
B
A
B
A
B
A
B
n
H
L
L
L
X
X
L
L
L
L
L
H
L
e
Word A
Word B
l
Word A Word B
L
H
L
l
Word B Word A
H
L
l
Tying the A
B output from one device into an A input on
k
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
another device and the A B output into the corresponding
B input permits easy expansion.
X
The A4 and B4 inputs are the most significant inputs and
A0, B0 the least significant. Thus if A4 is HIGH and B4 is
l
inputs except E.
LOW, the A
B output will be HIGH regardless of all other
Logic Symbol
TL/F/9792–2
e
e
V
Pin 16
CC
GND
Pin 6
3
NSC [ National Semiconductor ]
