Functional Description
The ’AC/’ACT175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or Data
inputs. The ’AC/’ACT175 is useful for general logic applica-
tions where a common Master Reset and Clock are
acceptable.
Truth Table
Inputs
@
t
n
, MR = H
Outputs
@
t
n+1
D
n
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
t
n
= Bit Time before Clock Pulse
t
n+1
= Bit Time after Clock Pulse
Q
n
L
H
Q
n
H
L
Logic Diagram
DS100278-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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