Functional Description (Continued)
State Diagrams
the TC signal is derived by decoding the flip-flop states,
there exists the possibility of decoding spikes on TC. For this
reason the use of TC as a clock signal is not recommended
(see logic equations below).
=
1. Count Enable CEP •CET • PE
=
2. Up: TC Q0•Q1•Q 2Q3•(Up)•CET
=
3. Down: TC Q0• Q1•Q2•Q3 •(Down)•CET
Mode Select Table
DS100276-6
PE
CEP CET
U/D
Action on Rising
Clock Edge
L
X
L
X
L
X
H
L
Load (Pn to Qn)
H
H
H
H
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
L
L
H
X
X
H
X
X
No Change (Hold)
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
3
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