欢迎访问ic37.com |
会员登录 免费注册
发布采购

54AC161F 参数 Datasheet PDF下载

54AC161F图片预览
型号: 54AC161F
PDF下载: 下载PDF文件 查看货源
内容描述: 同步可预置二进制计数器 [Synchronous Presettable Binary Counter]
分类和应用: 计数器
文件页数/大小: 12 页 / 195 K
品牌: NSC [ National Semiconductor ]
 浏览型号54AC161F的Datasheet PDF文件第1页浏览型号54AC161F的Datasheet PDF文件第3页浏览型号54AC161F的Datasheet PDF文件第4页浏览型号54AC161F的Datasheet PDF文件第5页浏览型号54AC161F的Datasheet PDF文件第6页浏览型号54AC161F的Datasheet PDF文件第7页浏览型号54AC161F的Datasheet PDF文件第8页浏览型号54AC161F的Datasheet PDF文件第9页  
The Terminal Count (TC) output is HIGH when CET is HIGH  
and counter is in state 15. To implement synchronous multi-  
stage counters, the TC outputs can be used with the CEP  
and CET inputs in two different ways.  
Connection Diagrams  
Pin Assignment  
for DIP and Flatpak  
Figure 1 shows the connections for simple ripple carry, in  
which the clock period must be longer than the CP to TC de-  
lay of the first stage, plus the cumulative CET to TC delays of  
the intermediate stages, plus the CET to CP setup time of  
the last stage. This total delay plus setup time sets the upper  
limit on clock frequency. For faster clock rates, the carry loo-  
kahead connections shown in Figure 2 are recommended. In  
this scheme the ripple delay through the intermediate stages  
commences with the same clock that causes the first stage  
to tick over from max to min in the Up mode, or min to max  
in the Down mode, to start its final cycle. Since this final  
cycle requires 16 clocks to complete, there is plenty of time  
for the ripple to progress through the intermediate stages.  
The critical timing that limits the clock period is the CP to TC  
delay of the first stage plus the CEP to CP setup time of the  
last stage. The TC output is subject to decoding spikes due  
to internal race conditions and is therefore not recom-  
DS100274-3  
Pin Assignment  
for LCC  
mended for use as  
a clock or asynchronous reset for  
flip-flops, registers or counters.  
=
Logic Equations: Count Enable CEP CET PE  
=
TC Q0 Q1 Q2 Q3 CET  
Mode Select Table  
PE  
CET  
CEP  
Action on the Rising  
N
Clock Edge (  
Reset (Clear)  
)
X
L
X
X
H
L
X
X
H
X
L
Load (Pn Qn)  
DS100274-4  
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
Functional Description  
X
The ’AC/’ACT161 count in modulo-16 binary sequence.  
From state 15 (HHHH) they increment to state 0 (LLLL). The  
clock inputs of all flip-flops are driven in parallel through a  
clock buffer. Thus all changes of the Q outputs (except due  
to Master Reset of the ’161) occur as a result of, and syn-  
chronous with, the LOW-to-HIGH transition of the CP input  
signal. The circuits have four fundamental modes of opera-  
tion, in order of precedence: asynchronous reset, parallel  
load, count-up and hold. Five control inputs — Master Reset,  
Parallel Enable (PE), Count Enable Parallel (CEP) and  
Count Enable Trickle (CET) — determine the mode of opera-  
tion, as shown in the Mode Select Table. A LOW signal on  
MR overrides all other inputs and asynchronously forces all  
outputs LOW. A LOW signal on PE overrides counting and  
allows information on the Parallel Data (Pn) inputs to be  
loaded into the flip-flops on the next rising edge of CP. With  
PE and MR HIGH, CEP and CET permit counting when both  
are HIGH. Conversely, a LOW signal on either CEP or CET  
inhibits counting.  
=
=
=
H
L
X
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
State Diagram  
The ’AC/’ACT161 use D-type edge-triggered flip-flops and  
changing the PE, CEP and CET inputs when the CP is in ei-  
ther state does not cause errors, provided that the recom-  
mended setup and hold times, with respect to the rising edge  
of CP, are observed.  
DS100274-5  
www.national.com  
2