Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100267-3
DS100267-4
Truth Table
(each half)
Inputs
Outputs
SD
L
CD
H
L
CP
X
J
X
X
X
L
K
X
X
X
L
Q
Q
L
H
L
H
L
X
H
H
H
L
X
H
L
N
N
N
N
H
H
H
H
H
H
H
H
H
H
H
L
L
Toggle
H
H
X
Q0
H
Q0
L
H
X
L
Q0
Q0
=
=
H
L
HIGH Voltage Level
LOW Voltage Level
N =
LOW-to-HIGH Transition
Immaterial
=
X
=
Q (Q ) Previous Q (Q ) before LOW-to-HIGH Transition of Clock
0
0
0
0
Logic Diagram (one half shown)
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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