Pin Descriptions
Pin Names
A0–A7
Description
Data Register A Inputs/TRI-STATE Outputs
Data Register B Inputs/TRI-STATE Outputs
Clock Pulse Inputs
B0–B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Select Inputs
Output Enable Inputs
Logic Diagram
DS100220-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Functional Description
In the transceiver mode, data present at the HIGH imped-
ate Clock Inputs (CPAB, CPBA) regardless of the Select or
Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output rein-
forces its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.
ance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamental
bus-management functions that can be performed with the
’ABT652C.
Data on the A or B data bus, or both can be stored in the in-
ternal D flip-flop by LOW to HIGH transitions at the appropri-
3
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