Pin Descriptions
Functional Description
The ’ABT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Pin
Description
Names
D0–D7
CP
Data Inputs
Clock Pulse Input (Active
Rising Edge)
OE
TRI-STATE Output Enable
Input (Active LOW)
O0–O7
TRI-STATE Outputs
Function Table
Inputs
CP
H
Internal
Outputs
Function
OE
H
H
H
H
L
D
L
Q
NC
NC
L
O
Z
Hold
Hold
Load
Load
H
H
L
Z
N
Z
N
H
L
H
Z
N
L
L
Data Available
N
L
H
L
H
H
Data Available
L
H
H
NC
NC
NC
NC
No Change in Data
No Change in Data
L
H
=
=
=
=
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
N =
LOW-to-HIGH Transition
=
NC No Change
Logic Diagram
DS100207-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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