Connection Diagrams
Pin Assignment for DIP
and Flatpack
Pin Assignment
for LCC
DS100205-2
DS100205-1
Pin
Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Description
Data Inputs
Master Reset
(Active LOW)
Clock Pulse Input
(Active Rising Edge)
Data Outputs
H = HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
sition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
sition
X = Immaterial
N
= LOW-to-HIGH clock transition
Truth Table
Mode Select-Function Table
Operating Mode
MR
Reset (Clear)
Load “1”
Load “0”
L
H
H
Inputs
CP
X
N
N
Output
D
n
X
h
l
Q
n
L
H
L
Logic Diagram
DS100205-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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