Functional Description
The ’97 contains six JK flip-flops connected as a synchro-
nous modulo-64 binary counter. A LOW signal on the Count
Enable (CE) input permits counting, with all state changes
initiated simultaneously by the rising edge of the clock.
When the count reaches maximum (63), with all Qs HIGH,
the Terminal Count (TC) output will be LOW if CE is LOW. A
HIGH signal on Master Reset (MR) resets the flip-flops and
prevents counting, although output pulses can still occur if
ing pulses passed by two or more of the AND gates. The
Pulse Pattern Table indicates the output pattern for several
values of m. In each row, a one means that the O output
Z
will be HIGH during that entire clock period, while a zero
means that O will be LOW when the clock is LOW in that
Z
period. The first column in the output field coincides with the
‘‘all zeroes’’ condition of the counter, while the last column
represents the ‘‘all ones’’ condition. The pulse pattern for
any particular value of m can be deduced by factoring it into
the clock is running, E is LOW and S5 is HIGH.
Z
e
a a
2
the sum of appropriate powers of two (e.g. 19
1) and combining the pulses (i.e., the zeroes) shown for
16
The flip-flop outputs are decoded by a 6-wide AND-OR-IN-
VERT gate. Each AND gate also contains the buffered and
inverted CP and Z-enable (E ) functions, as well as one of
e
each for the relevant powers of two (e.g. for m
1).
16, 2 and
Z
the Select (S0–S5) inputs. The Z output, O is normally
Z
HIGH and goes LOW when CP and E are LOW and any of
Z
The Y output O is the complement of O and is thus nor-
Y Z
the AND gates has its other inputs HIGH. The AND gates
are enabled by the counter at different times and different
rates relative to the clock. For example, the gate to which
S5 is connected is enabled during every other clock period,
assuming S5 is HIGH. Thus, during one complete cycle of
the counter (64 clocks) the S5 gate is enabled 32 times and
can therefore gate 32 clocks per cycle to the output. The S4
gate is enabled 16 times per cycle, the S3 gate 8 times per
cycle, etc. The output pulse rate thus depends on the clock
rate and which of the S0–S5 inputs is HIGH.
mally LOW. A LOW signal on the Y-enable input, E , dis-
Y
ables O . To expand the multiplier to 12-bit rate select, two
y
packages can be cascaded as shown in Figure A. Both cir-
cuits operate from the basic clock, with the TC output of the
first acting to enable both counting and the output pulses of
the second package. Thus the second counter advances at
only (/64 the rate of the first and a full cycle of the two coun-
ters combined requires 4096 clocks. Each rate select input
of the first package has 64 times the weight of its counter-
part in the second package.
a
m
2
m
m
1
e
e
f
f
f
f
in
#
#
out
in
out
64
4
64 64
#
5
1
2
2
11
10
9
8
2
e
a
a
a
a
a
e
a
a
a
a
(first package)
a
a
a
Where: m
S5
2
2
S4
S0
2
S3
2
3
S2
S1
Where: m
S5
S1
S5
2
2
2
S4
S0
S4
2
2
S3
2
S2
S2
#
#
#
#
#
#
#
#
#
#
#
#
#
1
0
7
6
4
2
5
3
e
S0
a
a
2
2
m
1
2
S3
2
#
#
#
2
Thus by appropriate choice of signals applied to the S0–S5
inputs, the output pulse rate can range from (/64 to $*/64 of
the clock rate, as suggested in Rate Select Table. There is
no output pulse when the counter is in the ‘‘all ones’’ condi-
tion. When m is 1, 2, 4, 8, 16 or 32, the output pulses are
evenly spaced, assuming that the clock frequency is con-
stant. For any other value of m the output pulses are not
evenly spaced, since the pulse train is formed by interleav-
0
a
S1
2
2
(second package)
#
#
Combined output pulses are obtained in Figure A by letting
the Z output of the first circuit act as the Y-enable function
for the second, with the interleaved pulses obtained from
the Y output of the second package being opposite in phase
to the clock.
TL/F/9780–3
FIGURE A. Cascading for 12-Bit Rate Select
4
NSC [ National Semiconductor ]
