5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier
June 1989
5497 DM7497
Synchronous Modulo-64 Bit Rate Multiplier
General Description
The ’97 contains a synchronous 6-stage binary counter and
six decoding gates that serve to gate the clock through to
the output at a sub-multiple of the input frequency The out-
put pulse rate relative to the clock frequency is determined
by signals applied to the Select (S0–S5) inputs Both true
and complement outputs are available along with an enable
input for each A Count Enable input and a Terminal Count
output are provided for cascading two or more packages
An asynchronous Master Reset input prevents counting and
resets the counter
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 9780 – 2
TL F 9780 – 1
V
CC
e
Pin 16
GND
e
Pin 8
Order Number 5497DMQB 5497FMQB or DM7497N
See NS Package Number J16A N16E or W16A
Pin Names
S0–S5
E
Z
E
Y
CE
CP
MR
O
Z
O
y
TC
Description
Rate Select Inputs
O
Z
Enable Input (Active LOW)
O
Y
Enable Input
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Gated Clock Output (Active LOW)
Complement Output (Active HIGH)
Terminal Count Output (Active LOW)
C
1995 National Semiconductor Corporation
TL F 9780
RRD-B30M115 Printed in U S A
NSC [ NATIONAL SEMICONDUCTOR ]
