e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
e
e
L
From (Input)
To (Output)
R
400X, C
15 pF
Max
L
Symbol
Parameter
Units
Min
f
t
Maximum Clock Frequency
25
MHz
ns
MAX
Propagation Delay Time
High to Low Level Output
Clock to
Output
PHL
35
35
t
Propagation Delay Time
Low to High Level Output
Clock to
Output
PLH
ns
Function Table
Inputs
Serial
Outputs
Mode
Clocks
Parallel
Q
A
Q
Q
Q
D
B
C
Control
2(L)
1(R)
A
B
C
D
H
H
H
v
v
L
X
X
X
X
X
X
H
L
X
a
X
b
X
c
X
d
Q
Q
Q
Q
D0
A0
a
B0
b
C0
c
d
d
H
X
Q
B
Q
C
X
Q
D
X
d
Q
Q
Q
²
²
²
Bn
A0
Cn
B0
An
An
B0
B0
B0
B0
B0
Dn
C0
Bn
Bn
C0
C0
C0
C0
C0
L
H
v
v
L
X
X
X
X
X
X
X
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
D0
Cn
Cn
D0
D0
D0
D0
D0
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
Q
Q
Q
Q
Q
Q
Q
L
X
L
L
X
X
X
X
X
Q
u
v
v
u
u
A0
A0
A0
A0
A0
L
L
Q
Q
Q
Q
L
H
L
H
H
H
²
Shifting left requires external connection of Q to A, Q to B, Q to C. Serial data is entered at input D.
B
C
D
e
e
e
Low Level (Steady State), X Don’t Care (Any input, including transitions)
H
High Level (Steady State), L
e
e
Transition from high to low level,
Transition from low to high level
v
a, b, c, d
u
The level of steady, state input at inputs A, B, C, or D, respectively.
e
e
e
Q
Q
, Q , Q , Q
B0 C0
The level of Q , Q , Q , Q , respectively, before the indicated steady state input conditions were established.
A B C D
A0
D0
Dn
, Q , Q , Q
Bn Cn
The level of Q , Q , Q , Q , respectively, before the most recent
C
transition of the clock.
v
An
A
B
D
Logic Diagram
TL/F/6534–2
3
NSC [ National Semiconductor ]
