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5476FMQB 参数 Datasheet PDF下载

5476FMQB图片预览
型号: 5476FMQB
PDF下载: 下载PDF文件 查看货源
内容描述: 双主从JK触发器与清除,预置和互补输出 [Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs]
分类和应用: 触发器逻辑集成电路
文件页数/大小: 4 页 / 111 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops
with Clear Preset and Complementary Outputs
June 1989
5476 DM5476 DM7476
Dual Master-Slave J-K Flip-Flops with Clear
Preset and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flop after a complete clock
pulse While the clock is low the slave is isolated from the
master On the positive transition of the clock the data from
the J and K inputs is transferred to the master While the
clock is high the J and K inputs are disabled On the nega-
tive transition of the clock the data from the master is trans-
ferred to the slave The logic state of J and K inputs must
not be allowed to change while the clock is high The data is
transfered to the outputs on the falling edge of the clock
pulse A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs
Features
Y
Alternate Military Aerospace device (5476) is available
Contact a National Semiconductor Sales Office Distrib-
utor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
Inputs
PR
L
H
L
H
H
H
H
CLR
H
L
L
H
H
H
H
CLK
X
X
X
J
X
X
X
L
H
L
H
K
X
X
X
L
L
H
H
Outputs
Q
Q
H
L
L
H
H
H
Q
0
Q
0
H
L
L
H
Toggle
H
e
High Logic Level
L
e
Low Logic Level
X
e
Either Low or High Logic Level
e
Positive pulse data The J and K inputs must be held constant while
the clock is high Data is transfered to the outputs on the falling edge of the
clock pulse
TL F 6528 – 1
Order Number 5476DMQB 5476FMQB
DM5476J DM5476W or DM7476N
See NS Package Number J16A N16E or W16A
e
This configuration is nonstable that is it will not persist when the preset
and or clear inputs return to their inactive (high) level
Q
0
e
The output logic level before the indicated input conditions were es-
tablished
Toggle
e
Each output changes to the complement of its previous level on
each complete active high level clock pulse
C
1995 National Semiconductor Corporation
TL F 6528
RRD-B30M105 Printed in U S A