e a
e a
25 C (See Section 1 for test waveforms and output load)
Switching Characteristics V
5.0V, T
§
CC
A
e
e
C
15 pF
L
Symbol
Parameter
R
400X
Units
L
Min
Max
t
t
Propagation Delay, CP to Q
27
32
PLH
n
ns
PHL
Functional Description
Truth Table
This device is a high speed quad 2-port register. It selects
four bits of data from two sources (ports) under the control
of a Common Select input (S). The selected data is trans-
ferred to the 4-bit output register synchronous with the
HIGH-to-LOW transition of the Clock input (CP). The 4-bit
Inputs
Output
S
I
0x
I
Q
x
1x
I
I
I
X
X
l
L
H
L
h
X
X
output register is fully edge-triggered. The Data inputs (I
)
nx
h
h
and Select input (S) need be stable only one setup time
prior to the HIGH-to-LOW transition of the clock for predict-
able operation.
h
H
e
l
LOW Voltage Level one setup time prior to the HIGH-to-LOWclock
transition.
e
h
HIGH Voltage Level one setup time prior to the HIGH-to-LOW clock
transition.
e
e
e
H
L
HIGH Voltage level
LOW Voltage level
Immaterial
X
Logic Diagram
TL/F/10215–3
3
NSC [ National Semiconductor ]
