2.0 Signal Definitions
This section describes the external interface of the Geode
GXLV processor. Figure 2-1 shows the signals organized
by their functional interface groups (internal test and elec-
trical pins are not shown).
SYSCLK
CLKMODE[2:0]
RESET
MD[63:0]
MA[12:0]
BA[1:0]
INTR
IRQ13
SMI#
RASA#, RASB#
CASA#, CASB#
CS[3:0]#
WEA#, WEB#
DQM[7:0]
CKEA, CKEB
SDCLK[3:0]
SDCLK_IN
SDCLK_OUT
System
Interface
Signals
Memory
Controller
Interface
Signals
SUSP#
SUSPA#
SERIALP
Geode™
AD[31:0]
C/BE[3:0]#
PAR
GXLV
PCLK
FRAME#
IRDY#
VID_CLK
DCLK
Processor
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
CRT_HSYNC
CRT_VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_RDY
PCI
Interface
Signals
Video
Interface
Signals
SERR#
REQ[2:0]#
GNT[2:0]#
VID_VAL
VID_DATA[7:0]
PIXEL[17:0]
Figure 2-1. Functional Block Diagram
Revision 1.1
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