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30151-33 参数 Datasheet PDF下载

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型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
Table 3-17. TR5-TR3 Bit Definitions  
Bit  
Name  
Description  
TR5 Register (R/W)  
11:4  
3:2  
Line Selection Line Selection:  
Physical address bits 11-4 used to select one of 256 lines.  
Set/DWORD Set/DWord Selection:  
Cache read: Selects which of the four sets in the cache is used as the source for data  
transferred to the cache flush buffer.  
Cache write: Selects which of the four sets in the cache is used as the destination for data transferred  
from the cache fill buffer.  
Flush buffer read: Selects which of the four Dword in the flush buffer is  
used during a TR3 read.  
Fill buffer write: Selects which of the four Dword in the fill buffer is written during a TR3 write.  
Control Bits:  
1:0  
Control Bits  
If = 00: flush read or fill buffer write.  
If = 01: cache write.  
If = 10: cache read.  
If = 11: cache flush.  
TR4 Register (R/W)  
31:12  
Upper Tag  
Upper Tag Address:  
Address  
Cache read: Upper 20 bits of tag address of the selected entry.  
Cache write: Data written into the upper 20 bits of the tag address of the selected entry.  
Valid Bit:  
10  
Valid Bit  
Cache read: Valid bit for the selected entry.  
Cache write: Data written into the valid bit for the selected entry.  
LRU Bits:  
9:7  
LRU Bits  
Cache read: The LRU bits for the selected line.  
xx1 = Set 0 or Set 1 most recently accessed.  
xx0 = Set 2 or Set 3 most recently accessed.  
x1x = Most recent access to Set 0 or Set 1 was to Set 0.  
x0x = Most recent access to Set 0 or Set 1 was to Set 1.  
1xx = Most recent access to Set 2 or Set 3 was to Set 2.  
0xx = Most recent access to Set 2 or Set 3 was to Set 3.  
Cache write: Ignored.  
6:3  
2:0  
Dirty Bits  
RSVD  
Dirty Bits:  
Cache read: The dirty bits for the selected entry (one bit per DWord).  
Cache write: Data written into the dirty bits for the selected entry.  
Reserved: Set to 0.  
TR3 Register (R/W)  
31:0  
Cache Data  
Cache Data:  
Flush buffer read: Data accessed from the cache flush buffer.  
Fill buffer write: Data to be written into the cache fill buffer.  
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