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30151-33 参数 Datasheet PDF下载

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型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.3.2.3 Debug Registers  
The Debug Address Registers (DR0-DR3) each contain  
the linear address for one of four possible breakpoints.  
Each breakpoint is further specified by bits in the Debug  
Control Register (DR7). For each breakpoint address in  
DR0-DR3, there are corresponding fields L, R/W, and  
LEN in DR7 that specify the type of memory access asso-  
ciated with the breakpoint.  
Six debug registers (DR0-DR3, DR6 and DR7) support  
debugging on the GXm processor. Memory addresses  
loaded in the debug registers, referred to as “breakpoints,”  
generate a debug exception when a memory access of  
the specified type occurs to the specified address. A  
breakpoint can be specified for a particular kind of mem-  
ory access such as a read or write operation. Code and  
data breakpoints can also be set allowing debug excep-  
tions to occur whenever a given data access (read or write  
operation) or code access (execute) occurs. The size of  
the debug target can be set to 1, 2, or 4 bytes. The debug  
registers are accessed through MOV instructions that can  
be executed only at privilege level 0 (real mode is always  
privilege level 0).  
The R/W field can be used to specify instruction execution  
as well as data access breakpoints. Instruction execution  
breakpoints are always taken before execution of the  
instruction that matches the breakpoint. The Debug Reg-  
isters are mapped in Table 3-12  
Table 3-12. Debug Registers  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
DR7 Register  
Debug Control Register 7 (R/W)  
LEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0  
0
0
G
D
0
0
1
1
1
0
0
G
3
L
3
G
2
L
2
G
1
L
1
G
0
L0  
DR6 Register  
Debug Status Register 6 (RO)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B
T
B
S
0
1
1
1
1
1
1
1
B3 B2 B1 B0  
DR3 Register‘  
DR2 Register  
DR1 Register  
DR0 Register  
Debug Address Register 3 (R/W))  
Breakpoint 3 Linear Address  
Debug Address Register 2 (R/W)  
Breakpoint 2 Linear Address  
Debug Address Register 1 (R/W)  
Breakpoint 1 Linear Address  
Debug Address Register 0 (R/W)  
Breakpoint 0 Linear Address  
Note: All bits marked as 0 or 1 are reserved and should not be modified.  
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