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30151-33 参数 Datasheet PDF下载

30151-33图片预览
型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
Table 3-11. Configuration Registers (Continued)  
Bit  
Name  
Description  
Index  
SMHR Bits  
SMM Header Address Bits [A31:0]: SMHR address bits [31:0] contain the physical base address  
for the SMM header space. For example, bits [31:24] correspond with Index B3h  
Refer to Section 3.11.4 “SMM Configuration Registers” on page 80 for more information.  
B3h  
B2h  
B1h  
B0h  
A[31:24]  
A[23:16]  
A[15:12]  
A[7:0]  
Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.  
Index CDh, CEh, CFh SMAR — SMM Address Region/Size Register (R/W)  
Default Value = 00h  
Index  
SMAR Bits  
SMM Address Region Bits [A31:A12]: SMAR address bits [31:12] contain the base address for  
the SMM region.  
Bits [31:24] correspond with Index CDh  
Bits [23:16] correspond with Index CEh  
Bits [15:12] correspond with Index CFh[7:4]  
CDh  
CEh  
CFh[7:4]  
A[31:24]  
A[23:16]  
A[15:12]  
Index CFh allows simultaneous access to SMAR address regions bits SMAR[15:12] and size code  
bits SIZE[3:0]. During access, the upper 4-bits of Port 23h hold SMAR[15:12].  
Refer to Section 3.11.4 “SMM Configuration Registers” on page 80 for more information.  
CFh[3:0]  
SIZE[3:0]  
SMM Region Size Bits [3:0]: SIZE bits contain the size code for the SMM region. During access  
the lower 4-bits of port 23 hold SIZE[3:0]. Index CFh allows simultaneous access to SMAR address  
regions bits SMAR[15:12] (see above) and size code bits.  
0000 = SMM Disabled  
0001 = 4 KB  
0010 = 8 KB  
0011 = 16 KB  
0001)  
0100 = 32 KB  
0101 = 64 KB  
0110 = 128 KB  
0111 = 256 KB  
1000 = 512 KB  
1001 = 1 MB  
1010 = 2 MB  
1011 = 4 MB  
1100 = 8 MB  
1101 = 16 MB  
1110 = 32 MB  
1111 = 4 KB (same as  
Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits.  
Index FEh  
DIR0 — Device Identification Register 0 (RO)  
Default Value = 4xh  
7:4  
3:0  
DID[3:0]  
Device ID (Read Only): Identifies device as GXm processor.  
MULT[3:0]  
Core Multiplier (Read Only) — Identifies the core multiplier set by the CLKMODE[2:0] pins (see  
signal descriptions page 21)  
If DIR1 (Index FFh) is 30h-4Fh then MULT[3:0]:  
0000 = SYSCLK multiplied by 4 (Test mode only)  
0001 = SYSCLK multiplied by 6  
0010 = SYSCLK multiplied by 4 (Test mode only)  
0011 = SYSCLK multiplied by 6  
0100 = SYSCLK multiplied by 7  
0101 = SYSCLK multiplied by 8  
0110 = SYSCLK multiplied by 7  
0111 = SYSCLK multiplied by 5  
1xxx = Reserved  
If DIR1 (Index FFh) is 50h or greater then MULT[3:0]:  
0000 = SYSCLK multiplied by 4 (Test mode only)  
0001 = SYSCLK multiplied by 10  
0010 = SYSCLK multiplied by 4 (Test mode only)  
0011 = SYSCLK multiplied by 6  
0100 = SYSCLK multiplied by 9  
0101 = SYSCLK multiplied by 5  
0110 = SYSCLK multiplied by 7  
0111 = SYSCLK multiplied by 8  
1xxx = Reserved  
Index FFh  
DIR1 -- Device Identification Register 1 (RO)  
Default Value = xxh  
7:0  
DIR1  
Device Identification Revision (Read Only) — DIR1 indicates device revision number.  
If DIR1 is 30h-33h = GXm processor revision 1.0 - 2.3  
If DIR1 is 34h-4Fh = GXm processor revision 2.4 - 3.x  
If DIR1 is 50h or greater = GXm processor revision 5.0 - 5.4..  
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